Hal Finkel c6940d4cb7 [PowerPC] Use VSX vector load/stores for v2[fi]64 ...

These instructions have access to the complete VSX register file. In addition,
they "swap" the order of the elements so that element 0 (the scalar part) comes
first in memory and element 1 follows at a higher address.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204838 91177308-0d34-0410-b5e6-96231b3b80d8

2014-03-26 18:26:30 +00:00

..

AArch64

AArch64_BE Elf support for MC-JIT runtime dynamic linker

2014-03-26 14:57:32 +00:00

ARM

ARM: add intrinsics for the v8 ldaex/stlex

2014-03-26 14:39:31 +00:00

CPP

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Generic

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Hexagon

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Inputs

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Mips

Add @llvm.clear_cache builtin

2014-03-26 12:52:28 +00:00

MSP430

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NVPTX

Add test to test/CodeGen/NVPTX for "alloca buffer" arguments.

2014-03-24 16:52:30 +00:00

PowerPC

[PowerPC] Use VSX vector load/stores for v2[fi]64

2014-03-26 18:26:30 +00:00

R600

R600: Add failing testcase for <3 x i32> stores.

2014-03-25 16:50:55 +00:00

SPARC

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SystemZ

[SystemZ] Add support for z196 float<->unsigned conversions

2014-03-21 10:56:30 +00:00

Thumb

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Thumb2

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X86

Fix for incorrect address sinking in the presence of potential overflows.

2014-03-26 17:27:01 +00:00

XCore

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