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187 lines
2.6 KiB
ReStructuredText
187 lines
2.6 KiB
ReStructuredText
tblgen - Target Description To C++ Code Generator
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=================================================
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SYNOPSIS
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--------
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**tblgen** [*options*] [*filename*]
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DESCRIPTION
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-----------
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**tblgen** translates from target description (.td) files into C++ code that can
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be included in the definition of an LLVM target library. Most users of LLVM will
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not need to use this program. It is only for assisting with writing an LLVM
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target backend.
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The input and output of **tblgen** is beyond the scope of this short
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introduction. Please see the *CodeGeneration* page in the LLVM documentation.
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The *filename* argument specifies the name of a Target Description (.td) file
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to read as input.
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OPTIONS
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-------
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**-help**
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Print a summary of command line options.
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**-o** *filename*
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Specify the output file name. If *filename* is ``-``, then **tblgen**
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sends its output to standard output.
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**-I** *directory*
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Specify where to find other target description files for inclusion. The
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*directory* value should be a full or partial path to a directory that contains
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target description files.
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**-asmparsernum** *N*
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Make -gen-asm-parser emit assembly writer number *N*.
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**-asmwriternum** *N*
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Make -gen-asm-writer emit assembly writer number *N*.
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**-class** *class Name*
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Print the enumeration list for this class.
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**-print-records**
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Print all records to standard output (default).
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**-print-enums**
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Print enumeration values for a class
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**-print-sets**
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Print expanded sets for testing DAG exprs.
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**-gen-emitter**
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Generate machine code emitter.
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**-gen-register-info**
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Generate registers and register classes info.
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**-gen-instr-info**
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Generate instruction descriptions.
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**-gen-asm-writer**
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Generate the assembly writer.
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**-gen-disassembler**
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Generate disassembler.
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**-gen-pseudo-lowering**
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Generate pseudo instruction lowering.
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**-gen-dag-isel**
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Generate a DAG (Directed Acycle Graph) instruction selector.
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**-gen-asm-matcher**
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Generate assembly instruction matcher.
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**-gen-dfa-packetizer**
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Generate DFA Packetizer for VLIW targets.
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**-gen-fast-isel**
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Generate a "fast" instruction selector.
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**-gen-subtarget**
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Generate subtarget enumerations.
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**-gen-intrinsic**
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Generate intrinsic information.
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**-gen-tgt-intrinsic**
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Generate target intrinsic information.
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**-gen-enhanced-disassembly-info**
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Generate enhanced disassembly info.
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**-version**
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Show the version number of this program.
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EXIT STATUS
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-----------
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If **tblgen** succeeds, it will exit with 0. Otherwise, if an error
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occurs, it will exit with a non-zero value.
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