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470c451574
GlobalAdderss nodes that appeared in more than one basic block were being counted twice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190078 91177308-0d34-0410-b5e6-96231b3b80d8
729 lines
27 KiB
C++
729 lines
27 KiB
C++
//===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief This is the parent TargetLowering class for hardware code gen
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/// targets.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUISelLowering.h"
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#include "AMDGPU.h"
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#include "AMDGPURegisterInfo.h"
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#include "AMDGPUSubtarget.h"
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#include "AMDILIntrinsicInfo.h"
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#include "R600MachineFunctionInfo.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/IR/DataLayout.h"
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using namespace llvm;
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#include "AMDGPUGenCallingConv.inc"
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AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
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TargetLowering(TM, new TargetLoweringObjectFileELF()) {
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// Initialize target lowering borrowed from AMDIL
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InitAMDILLowering();
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// We need to custom lower some of the intrinsics
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
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// Library functions. These default to Expand, but we have instructions
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// for them.
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setOperationAction(ISD::FCEIL, MVT::f32, Legal);
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setOperationAction(ISD::FEXP2, MVT::f32, Legal);
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setOperationAction(ISD::FPOW, MVT::f32, Legal);
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setOperationAction(ISD::FLOG2, MVT::f32, Legal);
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setOperationAction(ISD::FABS, MVT::f32, Legal);
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setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
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setOperationAction(ISD::FRINT, MVT::f32, Legal);
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// The hardware supports ROTR, but not ROTL
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setOperationAction(ISD::ROTL, MVT::i32, Expand);
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// Lower floating point store/load to integer store/load to reduce the number
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// of patterns in tablegen.
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setOperationAction(ISD::STORE, MVT::f32, Promote);
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AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
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setOperationAction(ISD::STORE, MVT::v2f32, Promote);
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AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
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setOperationAction(ISD::STORE, MVT::v4f32, Promote);
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AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
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setOperationAction(ISD::STORE, MVT::f64, Promote);
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AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
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// Custom lowering of vector stores is required for local address space
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// stores.
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setOperationAction(ISD::STORE, MVT::v4i32, Custom);
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// XXX: Native v2i32 local address space stores are possible, but not
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// currently implemented.
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setOperationAction(ISD::STORE, MVT::v2i32, Custom);
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setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
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setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
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setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
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// XXX: This can be change to Custom, once ExpandVectorStores can
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// handle 64-bit stores.
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setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
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setOperationAction(ISD::LOAD, MVT::f32, Promote);
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AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
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setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
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AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
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setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
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AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
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setOperationAction(ISD::LOAD, MVT::f64, Promote);
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AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
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setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
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setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
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setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Expand);
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setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Expand);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i8, Expand);
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setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand);
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setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Expand);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Expand);
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setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Expand);
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setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Expand);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand);
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setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Expand);
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setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Expand);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand);
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setOperationAction(ISD::FNEG, MVT::v2f32, Expand);
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setOperationAction(ISD::FNEG, MVT::v4f32, Expand);
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setOperationAction(ISD::MUL, MVT::i64, Expand);
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setOperationAction(ISD::UDIV, MVT::i32, Expand);
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setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
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setOperationAction(ISD::UREM, MVT::i32, Expand);
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setOperationAction(ISD::VSELECT, MVT::v2f32, Expand);
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setOperationAction(ISD::VSELECT, MVT::v4f32, Expand);
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static const MVT::SimpleValueType IntTypes[] = {
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MVT::v2i32, MVT::v4i32
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};
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const size_t NumIntTypes = array_lengthof(IntTypes);
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for (unsigned int x = 0; x < NumIntTypes; ++x) {
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MVT::SimpleValueType VT = IntTypes[x];
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//Expand the following operations for the current type by default
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setOperationAction(ISD::ADD, VT, Expand);
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setOperationAction(ISD::AND, VT, Expand);
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setOperationAction(ISD::FP_TO_SINT, VT, Expand);
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setOperationAction(ISD::FP_TO_UINT, VT, Expand);
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setOperationAction(ISD::MUL, VT, Expand);
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setOperationAction(ISD::OR, VT, Expand);
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setOperationAction(ISD::SHL, VT, Expand);
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setOperationAction(ISD::SINT_TO_FP, VT, Expand);
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setOperationAction(ISD::SRL, VT, Expand);
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setOperationAction(ISD::SRA, VT, Expand);
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setOperationAction(ISD::SUB, VT, Expand);
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setOperationAction(ISD::UDIV, VT, Expand);
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setOperationAction(ISD::UINT_TO_FP, VT, Expand);
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setOperationAction(ISD::UREM, VT, Expand);
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setOperationAction(ISD::VSELECT, VT, Expand);
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setOperationAction(ISD::XOR, VT, Expand);
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}
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static const MVT::SimpleValueType FloatTypes[] = {
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MVT::v2f32, MVT::v4f32
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};
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const size_t NumFloatTypes = array_lengthof(FloatTypes);
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for (unsigned int x = 0; x < NumFloatTypes; ++x) {
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MVT::SimpleValueType VT = FloatTypes[x];
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setOperationAction(ISD::FADD, VT, Expand);
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setOperationAction(ISD::FDIV, VT, Expand);
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setOperationAction(ISD::FFLOOR, VT, Expand);
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setOperationAction(ISD::FMUL, VT, Expand);
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setOperationAction(ISD::FRINT, VT, Expand);
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setOperationAction(ISD::FSUB, VT, Expand);
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}
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}
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//===----------------------------------------------------------------------===//
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// Target Information
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//===----------------------------------------------------------------------===//
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MVT AMDGPUTargetLowering::getVectorIdxTy() const {
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return MVT::i32;
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}
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//===---------------------------------------------------------------------===//
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// Target Properties
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//===---------------------------------------------------------------------===//
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bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
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assert(VT.isFloatingPoint());
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return VT == MVT::f32;
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}
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bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
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assert(VT.isFloatingPoint());
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return VT == MVT::f32;
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}
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//===---------------------------------------------------------------------===//
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// TargetLowering Callbacks
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//===---------------------------------------------------------------------===//
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void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
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const SmallVectorImpl<ISD::InputArg> &Ins) const {
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State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
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}
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SDValue AMDGPUTargetLowering::LowerReturn(
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SDValue Chain,
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CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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SDLoc DL, SelectionDAG &DAG) const {
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return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
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}
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//===---------------------------------------------------------------------===//
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// Target specific lowering
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//===---------------------------------------------------------------------===//
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SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
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const {
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switch (Op.getOpcode()) {
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default:
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Op.getNode()->dump();
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assert(0 && "Custom lowering code for this"
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"instruction is not implemented yet!");
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break;
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// AMDIL DAG lowering
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case ISD::SDIV: return LowerSDIV(Op, DAG);
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case ISD::SREM: return LowerSREM(Op, DAG);
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case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
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case ISD::BRCOND: return LowerBRCOND(Op, DAG);
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// AMDGPU DAG lowering
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case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
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case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
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case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
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case ISD::STORE: return LowerSTORE(Op, DAG);
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case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
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}
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return Op;
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}
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SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
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SDValue Op,
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SelectionDAG &DAG) const {
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const DataLayout *TD = getTargetMachine().getDataLayout();
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GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
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assert(G->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS);
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// XXX: What does the value of G->getOffset() mean?
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assert(G->getOffset() == 0 &&
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"Do not know what to do with an non-zero offset");
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const GlobalValue *GV = G->getGlobal();
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unsigned Offset;
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if (MFI->LocalMemoryObjects.count(GV) == 0) {
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uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
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Offset = MFI->LDSSize;
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MFI->LocalMemoryObjects[GV] = Offset;
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// XXX: Account for alignment?
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MFI->LDSSize += Size;
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} else {
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Offset = MFI->LocalMemoryObjects[GV];
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}
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return DAG.getConstant(Offset, getPointerTy(G->getAddressSpace()));
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}
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void AMDGPUTargetLowering::ExtractVectorElements(SDValue Op, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &Args,
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unsigned Start,
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unsigned Count) const {
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EVT VT = Op.getValueType();
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for (unsigned i = Start, e = Start + Count; i != e; ++i) {
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Args.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
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VT.getVectorElementType(),
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Op, DAG.getConstant(i, MVT::i32)));
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}
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}
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SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
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SelectionDAG &DAG) const {
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SmallVector<SDValue, 8> Args;
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SDValue A = Op.getOperand(0);
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SDValue B = Op.getOperand(1);
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ExtractVectorElements(A, DAG, Args, 0,
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A.getValueType().getVectorNumElements());
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ExtractVectorElements(B, DAG, Args, 0,
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B.getValueType().getVectorNumElements());
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return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(),
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&Args[0], Args.size());
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}
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SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
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SelectionDAG &DAG) const {
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SmallVector<SDValue, 8> Args;
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EVT VT = Op.getValueType();
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unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
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ExtractVectorElements(Op.getOperand(0), DAG, Args, Start,
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VT.getVectorNumElements());
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return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(),
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&Args[0], Args.size());
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}
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SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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SelectionDAG &DAG) const {
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unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
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SDLoc DL(Op);
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EVT VT = Op.getValueType();
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switch (IntrinsicID) {
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default: return Op;
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case AMDGPUIntrinsic::AMDIL_abs:
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return LowerIntrinsicIABS(Op, DAG);
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case AMDGPUIntrinsic::AMDIL_exp:
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return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
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case AMDGPUIntrinsic::AMDGPU_lrp:
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return LowerIntrinsicLRP(Op, DAG);
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case AMDGPUIntrinsic::AMDIL_fraction:
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return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
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case AMDGPUIntrinsic::AMDIL_max:
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return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
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Op.getOperand(2));
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case AMDGPUIntrinsic::AMDGPU_imax:
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return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
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Op.getOperand(2));
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case AMDGPUIntrinsic::AMDGPU_umax:
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return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
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Op.getOperand(2));
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case AMDGPUIntrinsic::AMDIL_min:
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return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
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Op.getOperand(2));
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case AMDGPUIntrinsic::AMDGPU_imin:
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return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
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Op.getOperand(2));
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case AMDGPUIntrinsic::AMDGPU_umin:
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return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
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Op.getOperand(2));
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case AMDGPUIntrinsic::AMDIL_round_nearest:
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return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
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}
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}
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///IABS(a) = SMAX(sub(0, a), a)
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SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
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SelectionDAG &DAG) const {
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SDLoc DL(Op);
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EVT VT = Op.getValueType();
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SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
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Op.getOperand(1));
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return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
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}
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/// Linear Interpolation
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/// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
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SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
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SelectionDAG &DAG) const {
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SDLoc DL(Op);
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EVT VT = Op.getValueType();
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SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
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DAG.getConstantFP(1.0f, MVT::f32),
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Op.getOperand(1));
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SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
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Op.getOperand(3));
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return DAG.getNode(ISD::FADD, DL, VT,
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DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
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OneSubAC);
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}
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/// \brief Generate Min/Max node
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SDValue AMDGPUTargetLowering::LowerMinMax(SDValue Op,
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SelectionDAG &DAG) const {
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SDLoc DL(Op);
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EVT VT = Op.getValueType();
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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SDValue True = Op.getOperand(2);
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SDValue False = Op.getOperand(3);
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SDValue CC = Op.getOperand(4);
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if (VT != MVT::f32 ||
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!((LHS == True && RHS == False) || (LHS == False && RHS == True))) {
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return SDValue();
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}
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ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
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switch (CCOpcode) {
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case ISD::SETOEQ:
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case ISD::SETONE:
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case ISD::SETUNE:
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case ISD::SETNE:
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case ISD::SETUEQ:
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case ISD::SETEQ:
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case ISD::SETFALSE:
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case ISD::SETFALSE2:
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case ISD::SETTRUE:
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case ISD::SETTRUE2:
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case ISD::SETUO:
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case ISD::SETO:
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assert(0 && "Operation should already be optimised !");
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case ISD::SETULE:
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case ISD::SETULT:
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case ISD::SETOLE:
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case ISD::SETOLT:
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case ISD::SETLE:
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case ISD::SETLT: {
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if (LHS == True)
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return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
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else
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return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);
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}
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case ISD::SETGT:
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case ISD::SETGE:
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case ISD::SETUGE:
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case ISD::SETOGE:
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case ISD::SETUGT:
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case ISD::SETOGT: {
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if (LHS == True)
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return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);
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else
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return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
|
|
}
|
|
case ISD::SETCC_INVALID:
|
|
assert(0 && "Invalid setcc condcode !");
|
|
}
|
|
return Op;
|
|
}
|
|
|
|
SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue &Op,
|
|
SelectionDAG &DAG) const {
|
|
LoadSDNode *Load = dyn_cast<LoadSDNode>(Op);
|
|
EVT MemEltVT = Load->getMemoryVT().getVectorElementType();
|
|
EVT EltVT = Op.getValueType().getVectorElementType();
|
|
EVT PtrVT = Load->getBasePtr().getValueType();
|
|
unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
|
|
SmallVector<SDValue, 8> Loads;
|
|
SDLoc SL(Op);
|
|
|
|
for (unsigned i = 0, e = NumElts; i != e; ++i) {
|
|
SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
|
|
DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8), PtrVT));
|
|
Loads.push_back(DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
|
|
Load->getChain(), Ptr,
|
|
MachinePointerInfo(Load->getMemOperand()->getValue()),
|
|
MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
|
|
Load->getAlignment()));
|
|
}
|
|
return DAG.getNode(ISD::BUILD_VECTOR, SL, Op.getValueType(), &Loads[0],
|
|
Loads.size());
|
|
}
|
|
|
|
SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
|
|
SelectionDAG &DAG) const {
|
|
StoreSDNode *Store = dyn_cast<StoreSDNode>(Op);
|
|
EVT MemVT = Store->getMemoryVT();
|
|
unsigned MemBits = MemVT.getSizeInBits();
|
|
|
|
// Byte stores are really expensive, so if possible, try to pack
|
|
// 32-bit vector truncatating store into an i32 store.
|
|
// XXX: We could also handle optimize other vector bitwidths
|
|
if (!MemVT.isVector() || MemBits > 32) {
|
|
return SDValue();
|
|
}
|
|
|
|
SDLoc DL(Op);
|
|
const SDValue &Value = Store->getValue();
|
|
EVT VT = Value.getValueType();
|
|
const SDValue &Ptr = Store->getBasePtr();
|
|
EVT MemEltVT = MemVT.getVectorElementType();
|
|
unsigned MemEltBits = MemEltVT.getSizeInBits();
|
|
unsigned MemNumElements = MemVT.getVectorNumElements();
|
|
EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), MemVT.getSizeInBits());
|
|
SDValue Mask;
|
|
switch(MemEltBits) {
|
|
case 8:
|
|
Mask = DAG.getConstant(0xFF, PackedVT);
|
|
break;
|
|
case 16:
|
|
Mask = DAG.getConstant(0xFFFF, PackedVT);
|
|
break;
|
|
default:
|
|
llvm_unreachable("Cannot lower this vector store");
|
|
}
|
|
SDValue PackedValue;
|
|
for (unsigned i = 0; i < MemNumElements; ++i) {
|
|
EVT ElemVT = VT.getVectorElementType();
|
|
SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
|
|
DAG.getConstant(i, MVT::i32));
|
|
Elt = DAG.getZExtOrTrunc(Elt, DL, PackedVT);
|
|
Elt = DAG.getNode(ISD::AND, DL, PackedVT, Elt, Mask);
|
|
SDValue Shift = DAG.getConstant(MemEltBits * i, PackedVT);
|
|
Elt = DAG.getNode(ISD::SHL, DL, PackedVT, Elt, Shift);
|
|
if (i == 0) {
|
|
PackedValue = Elt;
|
|
} else {
|
|
PackedValue = DAG.getNode(ISD::OR, DL, PackedVT, PackedValue, Elt);
|
|
}
|
|
}
|
|
return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
|
|
MachinePointerInfo(Store->getMemOperand()->getValue()),
|
|
Store->isVolatile(), Store->isNonTemporal(),
|
|
Store->getAlignment());
|
|
}
|
|
|
|
SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
StoreSDNode *Store = cast<StoreSDNode>(Op);
|
|
EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
|
|
EVT EltVT = Store->getValue().getValueType().getVectorElementType();
|
|
EVT PtrVT = Store->getBasePtr().getValueType();
|
|
unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
|
|
SDLoc SL(Op);
|
|
|
|
SmallVector<SDValue, 8> Chains;
|
|
|
|
for (unsigned i = 0, e = NumElts; i != e; ++i) {
|
|
SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
|
|
Store->getValue(), DAG.getConstant(i, MVT::i32));
|
|
SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT,
|
|
Store->getBasePtr(),
|
|
DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8),
|
|
PtrVT));
|
|
Chains.push_back(DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
|
|
MachinePointerInfo(Store->getMemOperand()->getValue()),
|
|
MemEltVT, Store->isVolatile(), Store->isNonTemporal(),
|
|
Store->getAlignment()));
|
|
}
|
|
return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, &Chains[0], NumElts);
|
|
}
|
|
|
|
SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
|
|
SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
|
|
if (Result.getNode()) {
|
|
return Result;
|
|
}
|
|
|
|
StoreSDNode *Store = cast<StoreSDNode>(Op);
|
|
if (Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS &&
|
|
Store->getValue().getValueType().isVector()) {
|
|
return SplitVectorStore(Op, DAG);
|
|
}
|
|
return SDValue();
|
|
}
|
|
|
|
SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
SDLoc DL(Op);
|
|
EVT VT = Op.getValueType();
|
|
|
|
SDValue Num = Op.getOperand(0);
|
|
SDValue Den = Op.getOperand(1);
|
|
|
|
SmallVector<SDValue, 8> Results;
|
|
|
|
// RCP = URECIP(Den) = 2^32 / Den + e
|
|
// e is rounding error.
|
|
SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
|
|
|
|
// RCP_LO = umulo(RCP, Den) */
|
|
SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
|
|
|
|
// RCP_HI = mulhu (RCP, Den) */
|
|
SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
|
|
|
|
// NEG_RCP_LO = -RCP_LO
|
|
SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
|
|
RCP_LO);
|
|
|
|
// ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
|
|
SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
|
|
NEG_RCP_LO, RCP_LO,
|
|
ISD::SETEQ);
|
|
// Calculate the rounding error from the URECIP instruction
|
|
// E = mulhu(ABS_RCP_LO, RCP)
|
|
SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
|
|
|
|
// RCP_A_E = RCP + E
|
|
SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
|
|
|
|
// RCP_S_E = RCP - E
|
|
SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
|
|
|
|
// Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
|
|
SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
|
|
RCP_A_E, RCP_S_E,
|
|
ISD::SETEQ);
|
|
// Quotient = mulhu(Tmp0, Num)
|
|
SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
|
|
|
|
// Num_S_Remainder = Quotient * Den
|
|
SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);
|
|
|
|
// Remainder = Num - Num_S_Remainder
|
|
SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
|
|
|
|
// Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
|
|
SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
|
|
DAG.getConstant(-1, VT),
|
|
DAG.getConstant(0, VT),
|
|
ISD::SETGE);
|
|
// Remainder_GE_Zero = (Remainder >= 0 ? -1 : 0)
|
|
SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Remainder,
|
|
DAG.getConstant(0, VT),
|
|
DAG.getConstant(-1, VT),
|
|
DAG.getConstant(0, VT),
|
|
ISD::SETGE);
|
|
// Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
|
|
SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
|
|
Remainder_GE_Zero);
|
|
|
|
// Calculate Division result:
|
|
|
|
// Quotient_A_One = Quotient + 1
|
|
SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
|
|
DAG.getConstant(1, VT));
|
|
|
|
// Quotient_S_One = Quotient - 1
|
|
SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
|
|
DAG.getConstant(1, VT));
|
|
|
|
// Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
|
|
SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
|
|
Quotient, Quotient_A_One, ISD::SETEQ);
|
|
|
|
// Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
|
|
Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
|
|
Quotient_S_One, Div, ISD::SETEQ);
|
|
|
|
// Calculate Rem result:
|
|
|
|
// Remainder_S_Den = Remainder - Den
|
|
SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
|
|
|
|
// Remainder_A_Den = Remainder + Den
|
|
SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
|
|
|
|
// Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
|
|
SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
|
|
Remainder, Remainder_S_Den, ISD::SETEQ);
|
|
|
|
// Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
|
|
Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
|
|
Remainder_A_Den, Rem, ISD::SETEQ);
|
|
SDValue Ops[2];
|
|
Ops[0] = Div;
|
|
Ops[1] = Rem;
|
|
return DAG.getMergeValues(Ops, 2, DL);
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Helper functions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
|
|
if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
|
|
return CFP->isExactlyValue(1.0);
|
|
}
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
|
|
return C->isAllOnesValue();
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
|
|
if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
|
|
return CFP->getValueAPF().isZero();
|
|
}
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
|
|
return C->isNullValue();
|
|
}
|
|
return false;
|
|
}
|
|
|
|
SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
|
|
const TargetRegisterClass *RC,
|
|
unsigned Reg, EVT VT) const {
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
unsigned VirtualRegister;
|
|
if (!MRI.isLiveIn(Reg)) {
|
|
VirtualRegister = MRI.createVirtualRegister(RC);
|
|
MRI.addLiveIn(Reg, VirtualRegister);
|
|
} else {
|
|
VirtualRegister = MRI.getLiveInVirtReg(Reg);
|
|
}
|
|
return DAG.getRegister(VirtualRegister, VT);
|
|
}
|
|
|
|
#define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
|
|
|
|
const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
|
|
switch (Opcode) {
|
|
default: return 0;
|
|
// AMDIL DAG nodes
|
|
NODE_NAME_CASE(CALL);
|
|
NODE_NAME_CASE(UMUL);
|
|
NODE_NAME_CASE(DIV_INF);
|
|
NODE_NAME_CASE(RET_FLAG);
|
|
NODE_NAME_CASE(BRANCH_COND);
|
|
|
|
// AMDGPU DAG nodes
|
|
NODE_NAME_CASE(DWORDADDR)
|
|
NODE_NAME_CASE(FRACT)
|
|
NODE_NAME_CASE(FMAX)
|
|
NODE_NAME_CASE(SMAX)
|
|
NODE_NAME_CASE(UMAX)
|
|
NODE_NAME_CASE(FMIN)
|
|
NODE_NAME_CASE(SMIN)
|
|
NODE_NAME_CASE(UMIN)
|
|
NODE_NAME_CASE(URECIP)
|
|
NODE_NAME_CASE(EXPORT)
|
|
NODE_NAME_CASE(CONST_ADDRESS)
|
|
NODE_NAME_CASE(REGISTER_LOAD)
|
|
NODE_NAME_CASE(REGISTER_STORE)
|
|
NODE_NAME_CASE(LOAD_CONSTANT)
|
|
NODE_NAME_CASE(LOAD_INPUT)
|
|
NODE_NAME_CASE(SAMPLE)
|
|
NODE_NAME_CASE(SAMPLEB)
|
|
NODE_NAME_CASE(SAMPLED)
|
|
NODE_NAME_CASE(SAMPLEL)
|
|
NODE_NAME_CASE(STORE_MSKOR)
|
|
}
|
|
}
|