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assignment when selecting the def. This is the naive solution to the problem: insert a copy to the pre-chosen vreg. Other solutions might be preferable, such as: 1) Passing the dest reg into FastEmit_. However, this would require the higher level code to know about reg classes, which they don't currently. 2) Selecting blocks in reverse postorder. This has some compile time cost for computing the order, and we'd need to measure its impact. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55555 91177308-0d34-0410-b5e6-96231b3b80d8
236 lines
9.5 KiB
C++
236 lines
9.5 KiB
C++
//===-- FastISel.h - Definition of the FastISel class ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the FastISel class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_FASTISEL_H
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#define LLVM_CODEGEN_FASTISEL_H
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#include "llvm/BasicBlock.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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namespace llvm {
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class ConstantFP;
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class MachineBasicBlock;
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class MachineFunction;
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class MachineRegisterInfo;
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class TargetData;
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class TargetInstrInfo;
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class TargetLowering;
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class TargetMachine;
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class TargetRegisterClass;
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/// FastISel - This is a fast-path instruction selection class that
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/// generates poor code and doesn't support illegal types or non-trivial
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/// lowering, but runs quickly.
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class FastISel {
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protected:
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MachineBasicBlock *MBB;
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MachineFunction &MF;
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MachineRegisterInfo &MRI;
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const TargetMachine &TM;
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const TargetData &TD;
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const TargetInstrInfo &TII;
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const TargetLowering &TLI;
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public:
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/// SelectInstructions - Do "fast" instruction selection over the
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/// LLVM IR instructions in the range [Begin, N) where N is either
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/// End or the first unsupported instruction. Return N.
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/// ValueMap is filled in with a mapping of LLVM IR Values to
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/// virtual register numbers. MBB is a block to which to append
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/// the generated MachineInstrs.
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BasicBlock::iterator
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SelectInstructions(BasicBlock::iterator Begin, BasicBlock::iterator End,
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DenseMap<const Value *, unsigned> &ValueMap,
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DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap,
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MachineBasicBlock *MBB);
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/// TargetSelectInstruction - This method is called by target-independent
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/// code when the normal FastISel process fails to select an instruction.
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/// This gives targets a chance to emit code for anything that doesn't
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/// fit into FastISel's framework. It returns true if it was successful.
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///
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virtual bool
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TargetSelectInstruction(Instruction *I,
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DenseMap<const Value *, unsigned> &ValueMap,
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DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap,
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MachineBasicBlock *MBB) = 0;
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virtual ~FastISel();
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protected:
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explicit FastISel(MachineFunction &mf);
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/// FastEmit_r - This method is called by target-independent code
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/// to request that an instruction with the given type and opcode
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/// be emitted.
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virtual unsigned FastEmit_(MVT::SimpleValueType VT,
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MVT::SimpleValueType RetVT,
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ISD::NodeType Opcode);
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/// FastEmit_r - This method is called by target-independent code
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/// to request that an instruction with the given type, opcode, and
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/// register operand be emitted.
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///
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virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
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MVT::SimpleValueType RetVT,
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ISD::NodeType Opcode, unsigned Op0);
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/// FastEmit_rr - This method is called by target-independent code
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/// to request that an instruction with the given type, opcode, and
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/// register operands be emitted.
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///
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virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
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MVT::SimpleValueType RetVT,
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ISD::NodeType Opcode,
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unsigned Op0, unsigned Op1);
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/// FastEmit_ri - This method is called by target-independent code
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/// to request that an instruction with the given type, opcode, and
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/// register and immediate operands be emitted.
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///
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virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
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MVT::SimpleValueType RetVT,
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ISD::NodeType Opcode,
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unsigned Op0, uint64_t Imm);
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/// FastEmit_rf - This method is called by target-independent code
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/// to request that an instruction with the given type, opcode, and
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/// register and floating-point immediate operands be emitted.
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///
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virtual unsigned FastEmit_rf(MVT::SimpleValueType VT,
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MVT::SimpleValueType RetVT,
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ISD::NodeType Opcode,
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unsigned Op0, ConstantFP *FPImm);
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/// FastEmit_rri - This method is called by target-independent code
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/// to request that an instruction with the given type, opcode, and
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/// register and immediate operands be emitted.
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///
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virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
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MVT::SimpleValueType RetVT,
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ISD::NodeType Opcode,
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unsigned Op0, unsigned Op1, uint64_t Imm);
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/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
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/// to emit an instruction with an immediate operand using FastEmit_ri.
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/// If that fails, it materializes the immediate into a register and try
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/// FastEmit_rr instead.
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unsigned FastEmit_ri_(MVT::SimpleValueType VT,
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ISD::NodeType Opcode,
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unsigned Op0, uint64_t Imm,
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MVT::SimpleValueType ImmType);
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/// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
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/// to emit an instruction with an immediate operand using FastEmit_rf.
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/// If that fails, it materializes the immediate into a register and try
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/// FastEmit_rr instead.
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unsigned FastEmit_rf_(MVT::SimpleValueType VT,
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ISD::NodeType Opcode,
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unsigned Op0, ConstantFP *FPImm,
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MVT::SimpleValueType ImmType);
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/// FastEmit_i - This method is called by target-independent code
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/// to request that an instruction with the given type, opcode, and
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/// immediate operand be emitted.
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virtual unsigned FastEmit_i(MVT::SimpleValueType VT,
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MVT::SimpleValueType RetVT,
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ISD::NodeType Opcode,
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uint64_t Imm);
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/// FastEmit_f - This method is called by target-independent code
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/// to request that an instruction with the given type, opcode, and
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/// floating-point immediate operand be emitted.
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virtual unsigned FastEmit_f(MVT::SimpleValueType VT,
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MVT::SimpleValueType RetVT,
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ISD::NodeType Opcode,
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ConstantFP *FPImm);
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/// FastEmitInst_ - Emit a MachineInstr with no operands and a
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/// result register in the given register class.
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///
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unsigned FastEmitInst_(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC);
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/// FastEmitInst_r - Emit a MachineInstr with one register operand
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/// and a result register in the given register class.
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///
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unsigned FastEmitInst_r(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0);
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/// FastEmitInst_rr - Emit a MachineInstr with two register operands
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/// and a result register in the given register class.
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///
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unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, unsigned Op1);
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/// FastEmitInst_ri - Emit a MachineInstr with two register operands
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/// and a result register in the given register class.
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///
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unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, uint64_t Imm);
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/// FastEmitInst_rf - Emit a MachineInstr with two register operands
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/// and a result register in the given register class.
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///
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unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, ConstantFP *FPImm);
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/// FastEmitInst_rri - Emit a MachineInstr with two register operands,
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/// an immediate, and a result register in the given register class.
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///
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unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, unsigned Op1, uint64_t Imm);
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/// FastEmitInst_i - Emit a MachineInstr with a single immediate
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/// operand, and a result register in the given register class.
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unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
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const TargetRegisterClass *RC,
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uint64_t Imm);
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/// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
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/// from a specified index of a superregister.
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unsigned FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx);
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private:
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unsigned getRegForValue(Value *V,
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DenseMap<const Value*, unsigned> &ValueMap);
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unsigned createResultReg(const TargetRegisterClass *RC);
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bool SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
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DenseMap<const Value*, unsigned> &ValueMap);
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bool SelectGetElementPtr(Instruction *I,
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DenseMap<const Value*, unsigned> &ValueMap);
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bool SelectBitCast(Instruction *I,
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DenseMap<const Value*, unsigned> &ValueMap);
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bool SelectCast(Instruction *I, ISD::NodeType Opcode,
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DenseMap<const Value*, unsigned> &ValueMap);
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void UpdateValueMap(Instruction* I, unsigned Reg,
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DenseMap<const Value*, unsigned> &ValueMap);
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};
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}
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#endif
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