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34faf78241
Make a call to R600's implementation of verifyInstruction() to check that instructions are only using legal operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202544 91177308-0d34-0410-b5e6-96231b3b80d8
127 lines
4.1 KiB
C++
127 lines
4.1 KiB
C++
//===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
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//
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//===----------------------------------------------------------------------===//
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//
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#include "AMDGPUMCInstLower.h"
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#include "AMDGPUAsmPrinter.h"
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#include "InstPrinter/AMDGPUInstPrinter.h"
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#include "R600InstrInfo.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCObjectStreamer.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/Format.h"
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#include <algorithm>
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using namespace llvm;
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AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx):
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Ctx(ctx)
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{ }
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void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
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OutMI.setOpcode(MI->getOpcode());
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for (unsigned i = 0, e = MI->getNumExplicitOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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MCOperand MCOp;
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switch (MO.getType()) {
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default:
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llvm_unreachable("unknown operand type");
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case MachineOperand::MO_FPImmediate: {
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const APFloat &FloatValue = MO.getFPImm()->getValueAPF();
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assert(&FloatValue.getSemantics() == &APFloat::IEEEsingle &&
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"Only floating point immediates are supported at the moment.");
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MCOp = MCOperand::CreateFPImm(FloatValue.convertToFloat());
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break;
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}
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case MachineOperand::MO_Immediate:
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MCOp = MCOperand::CreateImm(MO.getImm());
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break;
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case MachineOperand::MO_Register:
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MCOp = MCOperand::CreateReg(MO.getReg());
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break;
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case MachineOperand::MO_MachineBasicBlock:
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MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
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MO.getMBB()->getSymbol(), Ctx));
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}
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OutMI.addOperand(MCOp);
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}
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}
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void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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AMDGPUMCInstLower MCInstLowering(OutContext);
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#ifdef _DEBUG
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StringRef Err;
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if (!TM.getInstrInfo()->verifyInstruction(MI, Err)) {
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errs() << "Warning: Illegal instruction detected: " << Err << "\n";
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MI->dump();
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}
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#endif
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if (MI->isBundle()) {
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const MachineBasicBlock *MBB = MI->getParent();
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MachineBasicBlock::const_instr_iterator I = MI;
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++I;
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while (I != MBB->end() && I->isInsideBundle()) {
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EmitInstruction(I);
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++I;
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}
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} else {
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MCInst TmpInst;
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MCInstLowering.lower(MI, TmpInst);
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EmitToStreamer(OutStreamer, TmpInst);
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if (DisasmEnabled) {
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// Disassemble instruction/operands to text.
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DisasmLines.resize(DisasmLines.size() + 1);
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std::string &DisasmLine = DisasmLines.back();
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raw_string_ostream DisasmStream(DisasmLine);
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AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(), *TM.getInstrInfo(),
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*TM.getRegisterInfo());
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InstPrinter.printInst(&TmpInst, DisasmStream, StringRef());
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// Disassemble instruction/operands to hex representation.
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SmallVector<MCFixup, 4> Fixups;
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SmallVector<char, 16> CodeBytes;
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raw_svector_ostream CodeStream(CodeBytes);
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MCObjectStreamer &ObjStreamer = (MCObjectStreamer &)OutStreamer;
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MCCodeEmitter &InstEmitter = ObjStreamer.getAssembler().getEmitter();
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InstEmitter.EncodeInstruction(TmpInst, CodeStream, Fixups,
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TM.getSubtarget<MCSubtargetInfo>());
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CodeStream.flush();
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HexLines.resize(HexLines.size() + 1);
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std::string &HexLine = HexLines.back();
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raw_string_ostream HexStream(HexLine);
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for (size_t i = 0; i < CodeBytes.size(); i += 4) {
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unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i];
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HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord);
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}
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DisasmStream.flush();
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DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size());
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}
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}
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}
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