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https://github.com/c64scene-ar/llvm-6502.git
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02d711b93e
instruction sequence and cannot ordinarily be simplified by DAGcombine into the various target description files or SPUDAGToDAGISel.cpp. This makes some 64-bit operations legal. - Eliminate target-dependent ISD enums. - Update tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61508 91177308-0d34-0410-b5e6-96231b3b80d8
84 lines
3.1 KiB
TableGen
84 lines
3.1 KiB
TableGen
//====--- SPU64InstrInfo.td - Cell SPU 64-bit operations -*- tablegen -*--====//
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//
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// Cell SPU 64-bit operations
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//
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// Primary author: Scott Michel (scottm@aero.org)
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//===----------------------------------------------------------------------===//
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// 64-bit comparisons:
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//
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// 1. The instruction sequences for vector vice scalar differ by a
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// constant. In the scalar case, we're only interested in the
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// top two 32-bit slots, whereas we're interested in an exact
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// all-four-slot match in the vector case.
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//
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// 2. There are no "immediate" forms, since loading 64-bit constants
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// could be a constant pool load.
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//
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// 3. i64 setcc results are i32, which are subsequently converted to a FSM
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// mask when used in a select pattern.
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//
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// 4. v2i64 setcc results are v4i32, which can be converted to a FSM mask (TODO)
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// [Note: this may be moot, since gb produces v4i32 or r32.]
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//
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// M00$E B!tes Kan be Pretty N@sTi!!!!! (appologies to Monty!)
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// selb instruction definition for i64. Note that the selection mask is
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// a vector, produced by various forms of FSM:
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def SELBr64_cond:
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SELBInst<(outs R64C:$rT), (ins R64C:$rA, R64C:$rB, VECREG:$rC),
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[/* no pattern */]>;
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// select the negative condition:
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class I64SELECTNegCond<PatFrag cond, CodeFrag compare>:
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Pat<(select (i32 (cond R64C:$rA, R64C:$rB)), R64C:$rTrue, R64C:$rFalse),
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(SELBr64_cond R64C:$rTrue, R64C:$rFalse, (FSMr32 compare.Fragment))>;
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// setcc the negative condition:
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class I64SETCCNegCond<PatFrag cond, CodeFrag compare>:
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Pat<(cond R64C:$rA, R64C:$rB),
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(XORIr32 compare.Fragment, -1)>;
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// The i64 seteq fragment that does the scalar->vector conversion and
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// comparison:
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def CEQr64compare:
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CodeFrag<(CGTIv4i32 (GBv4i32 (CEQv4i32 (ORv2i64_i64 R64C:$rA),
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(ORv2i64_i64 R64C:$rB))),
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0x0000000c)>;
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// The i64 seteq fragment that does the vector comparison
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def CEQv2i64compare:
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CodeFrag<(CGTIv4i32 (GBv4i32 (CEQv4i32 VECREG:$rA, VECREG:$rB)),
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0x0000000f)>;
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// i64 seteq (equality): the setcc result is i32, which is converted to a
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// vector FSM mask when used in a select pattern.
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//
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// v2i64 seteq (equality): the setcc result is v4i32
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multiclass CompareEqual64 {
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// Plain old comparison, converts back to i32 scalar
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def r64: CodeFrag<(ORi32_v4i32 CEQr64compare.Fragment)>;
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def v2i64: CodeFrag<(ORi32_v4i32 CEQv2i64compare.Fragment)>;
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// SELB mask from FSM:
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def r64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CEQr64compare.Fragment))>;
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def v2i64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CEQv2i64compare.Fragment))>;
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}
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defm I64EQ: CompareEqual64;
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def : Pat<(seteq R64C:$rA, R64C:$rB), I64EQr64.Fragment>;
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def : Pat<(seteq (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)), I64EQv2i64.Fragment>;
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def : Pat<(select R32C:$rC, R64C:$rB, R64C:$rA),
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(SELBr64_cond R64C:$rA, R64C:$rB, (FSMr32 R32C:$rC))>;
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// i64 setne:
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def : I64SETCCNegCond<setne, I64EQr64>;
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def : I64SELECTNegCond<setne, I64EQr64>;
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// i64 setugt:
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