llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-15 23:31:37 +00:00

History

Ahmed Bougacha 40453da779 [X86] 8bit divrem: Improve codegen for AH register extraction.

For 8-bit divrems where the remainder is used, we used to generate:
    divb  %sil
    shrw  $8, %ax
    movzbl  %al, %eax

That was to avoid an H-reg access, which is problematic mainly because
it isn't possible in REX-prefixed instructions.

This patch optimizes that to:
    divb  %sil
    movzbl  %ah, %eax

To do that, we explicitly extend AH, and extract the L-subreg in the
resulting register.  The extension is done using the NOREX variants of
MOVZX.  To support signed operations, MOVSX_NOREX is also added.
Further, this introduces a new SDNode type, [us]divrem_ext_hreg, which is
then lowered to a sequence containing a single zext (rather than 2).

Differential Revision: http://reviews.llvm.org/D6064


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221176 91177308-0d34-0410-b5e6-96231b3b80d8

2014-11-03 20:26:35 +00:00

Analysis

IR: MDNode => Value: Instruction::getMetadata()

2014-11-01 00:10:31 +00:00

AsmParser

X86: Implement the vectorcall calling convention

2014-10-28 01:29:26 +00:00

Bitcode

IR: MDNode => Value: Instruction::getAllMetadataOtherThanDebugLoc()

2014-11-03 18:13:57 +00:00

CodeGen

Normally an 'optnone' function goes through fast-isel, which does not