mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-10-30 16:17:05 +00:00
83815aeb29
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83667 91177308-0d34-0410-b5e6-96231b3b80d8
433 lines
11 KiB
LLVM
433 lines
11 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vshls8:
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;CHECK: vshl.u8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = shl <8 x i8> %tmp1, %tmp2
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vshls16:
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;CHECK: vshl.u16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = shl <4 x i16> %tmp1, %tmp2
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vshls32:
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;CHECK: vshl.u32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = shl <2 x i32> %tmp1, %tmp2
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ret <2 x i32> %tmp3
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}
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define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
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;CHECK: vshls64:
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;CHECK: vshl.u64
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%tmp1 = load <1 x i64>* %A
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%tmp2 = load <1 x i64>* %B
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%tmp3 = shl <1 x i64> %tmp1, %tmp2
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ret <1 x i64> %tmp3
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}
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define <8 x i8> @vshli8(<8 x i8>* %A) nounwind {
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;CHECK: vshli8:
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;CHECK: vshl.i8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = shl <8 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vshli16(<4 x i16>* %A) nounwind {
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;CHECK: vshli16:
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;CHECK: vshl.i16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = shl <4 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15 >
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vshli32(<2 x i32>* %A) nounwind {
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;CHECK: vshli32:
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;CHECK: vshl.i32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = shl <2 x i32> %tmp1, < i32 31, i32 31 >
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ret <2 x i32> %tmp2
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}
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define <1 x i64> @vshli64(<1 x i64>* %A) nounwind {
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;CHECK: vshli64:
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;CHECK: vshl.i64
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%tmp1 = load <1 x i64>* %A
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%tmp2 = shl <1 x i64> %tmp1, < i64 63 >
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ret <1 x i64> %tmp2
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}
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define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK: vshlQs8:
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;CHECK: vshl.u8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = shl <16 x i8> %tmp1, %tmp2
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ret <16 x i8> %tmp3
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}
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define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vshlQs16:
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;CHECK: vshl.u16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = shl <8 x i16> %tmp1, %tmp2
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK: vshlQs32:
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;CHECK: vshl.u32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = shl <4 x i32> %tmp1, %tmp2
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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;CHECK: vshlQs64:
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;CHECK: vshl.u64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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%tmp3 = shl <2 x i64> %tmp1, %tmp2
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ret <2 x i64> %tmp3
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}
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define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind {
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;CHECK: vshlQi8:
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;CHECK: vshl.i8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = shl <16 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind {
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;CHECK: vshlQi16:
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;CHECK: vshl.i16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = shl <8 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind {
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;CHECK: vshlQi32:
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;CHECK: vshl.i32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = shl <4 x i32> %tmp1, < i32 31, i32 31, i32 31, i32 31 >
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ret <4 x i32> %tmp2
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}
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define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind {
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;CHECK: vshlQi64:
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;CHECK: vshl.i64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = shl <2 x i64> %tmp1, < i64 63, i64 63 >
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ret <2 x i64> %tmp2
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}
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define <8 x i8> @vlshru8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vlshru8:
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;CHECK: vneg.s8
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;CHECK: vshl.u8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = lshr <8 x i8> %tmp1, %tmp2
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @vlshru16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vlshru16:
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;CHECK: vneg.s16
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;CHECK: vshl.u16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = lshr <4 x i16> %tmp1, %tmp2
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vlshru32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vlshru32:
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;CHECK: vneg.s32
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;CHECK: vshl.u32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = lshr <2 x i32> %tmp1, %tmp2
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ret <2 x i32> %tmp3
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}
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define <1 x i64> @vlshru64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
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;CHECK: vlshru64:
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;CHECK: vsub.i64
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;CHECK: vshl.u64
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%tmp1 = load <1 x i64>* %A
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%tmp2 = load <1 x i64>* %B
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%tmp3 = lshr <1 x i64> %tmp1, %tmp2
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ret <1 x i64> %tmp3
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}
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define <8 x i8> @vlshri8(<8 x i8>* %A) nounwind {
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;CHECK: vlshri8:
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;CHECK: vshr.u8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = lshr <8 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vlshri16(<4 x i16>* %A) nounwind {
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;CHECK: vlshri16:
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;CHECK: vshr.u16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = lshr <4 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16 >
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vlshri32(<2 x i32>* %A) nounwind {
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;CHECK: vlshri32:
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;CHECK: vshr.u32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = lshr <2 x i32> %tmp1, < i32 32, i32 32 >
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ret <2 x i32> %tmp2
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}
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define <1 x i64> @vlshri64(<1 x i64>* %A) nounwind {
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;CHECK: vlshri64:
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;CHECK: vshr.u64
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%tmp1 = load <1 x i64>* %A
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%tmp2 = lshr <1 x i64> %tmp1, < i64 64 >
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ret <1 x i64> %tmp2
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}
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define <16 x i8> @vlshrQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK: vlshrQu8:
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;CHECK: vneg.s8
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;CHECK: vshl.u8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = lshr <16 x i8> %tmp1, %tmp2
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ret <16 x i8> %tmp3
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}
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define <8 x i16> @vlshrQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vlshrQu16:
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;CHECK: vneg.s16
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;CHECK: vshl.u16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = lshr <8 x i16> %tmp1, %tmp2
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @vlshrQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK: vlshrQu32:
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;CHECK: vneg.s32
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;CHECK: vshl.u32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = lshr <4 x i32> %tmp1, %tmp2
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @vlshrQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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;CHECK: vlshrQu64:
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;CHECK: vsub.i64
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;CHECK: vshl.u64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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%tmp3 = lshr <2 x i64> %tmp1, %tmp2
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ret <2 x i64> %tmp3
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}
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define <16 x i8> @vlshrQi8(<16 x i8>* %A) nounwind {
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;CHECK: vlshrQi8:
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;CHECK: vshr.u8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = lshr <16 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @vlshrQi16(<8 x i16>* %A) nounwind {
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;CHECK: vlshrQi16:
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;CHECK: vshr.u16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = lshr <8 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vlshrQi32(<4 x i32>* %A) nounwind {
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;CHECK: vlshrQi32:
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;CHECK: vshr.u32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = lshr <4 x i32> %tmp1, < i32 32, i32 32, i32 32, i32 32 >
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ret <4 x i32> %tmp2
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}
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define <2 x i64> @vlshrQi64(<2 x i64>* %A) nounwind {
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;CHECK: vlshrQi64:
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;CHECK: vshr.u64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = lshr <2 x i64> %tmp1, < i64 64, i64 64 >
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ret <2 x i64> %tmp2
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}
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; Example that requires splitting and expanding a vector shift.
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define <2 x i64> @update(<2 x i64> %val) nounwind readnone {
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entry:
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%shr = lshr <2 x i64> %val, < i64 2, i64 2 > ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %shr
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}
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define <8 x i8> @vashrs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vashrs8:
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;CHECK: vneg.s8
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;CHECK: vshl.s8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = ashr <8 x i8> %tmp1, %tmp2
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @vashrs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vashrs16:
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;CHECK: vneg.s16
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;CHECK: vshl.s16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = ashr <4 x i16> %tmp1, %tmp2
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vashrs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vashrs32:
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;CHECK: vneg.s32
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;CHECK: vshl.s32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = ashr <2 x i32> %tmp1, %tmp2
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ret <2 x i32> %tmp3
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}
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define <1 x i64> @vashrs64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
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;CHECK: vashrs64:
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;CHECK: vsub.i64
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;CHECK: vshl.s64
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%tmp1 = load <1 x i64>* %A
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%tmp2 = load <1 x i64>* %B
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%tmp3 = ashr <1 x i64> %tmp1, %tmp2
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ret <1 x i64> %tmp3
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}
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define <8 x i8> @vashri8(<8 x i8>* %A) nounwind {
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;CHECK: vashri8:
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;CHECK: vshr.s8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = ashr <8 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vashri16(<4 x i16>* %A) nounwind {
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;CHECK: vashri16:
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;CHECK: vshr.s16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = ashr <4 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16 >
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vashri32(<2 x i32>* %A) nounwind {
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;CHECK: vashri32:
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;CHECK: vshr.s32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = ashr <2 x i32> %tmp1, < i32 32, i32 32 >
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ret <2 x i32> %tmp2
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}
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define <1 x i64> @vashri64(<1 x i64>* %A) nounwind {
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;CHECK: vashri64:
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;CHECK: vshr.s64
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%tmp1 = load <1 x i64>* %A
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%tmp2 = ashr <1 x i64> %tmp1, < i64 64 >
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ret <1 x i64> %tmp2
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}
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define <16 x i8> @vashrQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK: vashrQs8:
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;CHECK: vneg.s8
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;CHECK: vshl.s8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = ashr <16 x i8> %tmp1, %tmp2
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ret <16 x i8> %tmp3
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}
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define <8 x i16> @vashrQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vashrQs16:
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;CHECK: vneg.s16
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;CHECK: vshl.s16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = ashr <8 x i16> %tmp1, %tmp2
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @vashrQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK: vashrQs32:
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;CHECK: vneg.s32
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;CHECK: vshl.s32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = ashr <4 x i32> %tmp1, %tmp2
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @vashrQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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;CHECK: vashrQs64:
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;CHECK: vsub.i64
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;CHECK: vshl.s64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
|
|
%tmp3 = ashr <2 x i64> %tmp1, %tmp2
|
|
ret <2 x i64> %tmp3
|
|
}
|
|
|
|
define <16 x i8> @vashrQi8(<16 x i8>* %A) nounwind {
|
|
;CHECK: vashrQi8:
|
|
;CHECK: vshr.s8
|
|
%tmp1 = load <16 x i8>* %A
|
|
%tmp2 = ashr <16 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
|
|
ret <16 x i8> %tmp2
|
|
}
|
|
|
|
define <8 x i16> @vashrQi16(<8 x i16>* %A) nounwind {
|
|
;CHECK: vashrQi16:
|
|
;CHECK: vshr.s16
|
|
%tmp1 = load <8 x i16>* %A
|
|
%tmp2 = ashr <8 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
|
|
ret <8 x i16> %tmp2
|
|
}
|
|
|
|
define <4 x i32> @vashrQi32(<4 x i32>* %A) nounwind {
|
|
;CHECK: vashrQi32:
|
|
;CHECK: vshr.s32
|
|
%tmp1 = load <4 x i32>* %A
|
|
%tmp2 = ashr <4 x i32> %tmp1, < i32 32, i32 32, i32 32, i32 32 >
|
|
ret <4 x i32> %tmp2
|
|
}
|
|
|
|
define <2 x i64> @vashrQi64(<2 x i64>* %A) nounwind {
|
|
;CHECK: vashrQi64:
|
|
;CHECK: vshr.s64
|
|
%tmp1 = load <2 x i64>* %A
|
|
%tmp2 = ashr <2 x i64> %tmp1, < i64 64, i64 64 >
|
|
ret <2 x i64> %tmp2
|
|
}
|