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https://github.com/c64scene-ar/llvm-6502.git
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8fb06b3e8f
Changed tests which assumed that vectors are legalized by widening them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142152 91177308-0d34-0410-b5e6-96231b3b80d8
70 lines
1.9 KiB
LLVM
70 lines
1.9 KiB
LLVM
; RUN: llc -O1 --march=cellspu < %s | FileCheck %s
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;CHECK: shuffle
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define <4 x float> @shuffle(<4 x float> %param1, <4 x float> %param2) {
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; CHECK: cwd {{\$.}}, 0($sp)
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; CHECK: shufb {{\$., \$4, \$3, \$.}}
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%val= shufflevector <4 x float> %param1, <4 x float> %param2, <4 x i32> <i32 4,i32 1,i32 2,i32 3>
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ret <4 x float> %val
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}
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;CHECK: splat
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define <4 x float> @splat(float %param1) {
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; CHECK: lqa
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; CHECK: shufb $3
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; CHECK: bi
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%vec = insertelement <1 x float> undef, float %param1, i32 0
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%val= shufflevector <1 x float> %vec, <1 x float> undef, <4 x i32> <i32 0,i32 0,i32 0,i32 0>
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ret <4 x float> %val
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}
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;CHECK: test_insert
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define void @test_insert( <2 x float>* %ptr, float %val1, float %val2 ) {
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%sl2_17_tmp1 = insertelement <2 x float> zeroinitializer, float %val1, i32 0
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;CHECK: lqa $6,
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;CHECK: shufb $4, $4, $5, $6
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%sl2_17 = insertelement <2 x float> %sl2_17_tmp1, float %val2, i32 1
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;CHECK: cdd $5, 0($3)
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;CHECK: lqd $6, 0($3)
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;CHECK: shufb $4, $4, $6, $5
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;CHECK: stqd $4, 0($3)
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;CHECK: bi $lr
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store <2 x float> %sl2_17, <2 x float>* %ptr
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ret void
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}
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;CHECK: test_insert_1
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define <4 x float> @test_insert_1(<4 x float> %vparam, float %eltparam) {
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;CHECK: cwd $5, 4($sp)
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;CHECK: shufb $3, $4, $3, $5
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;CHECK: bi $lr
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%rv = insertelement <4 x float> %vparam, float %eltparam, i32 1
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ret <4 x float> %rv
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}
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;CHECK: test_v2i32
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define <2 x i32> @test_v2i32(<4 x i32>%vec)
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{
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;CHECK: rotqbyi $3, $3, 4
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;CHECK: bi $lr
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%rv = shufflevector <4 x i32> %vec, <4 x i32> undef, <2 x i32><i32 1,i32 2>
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ret <2 x i32> %rv
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}
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define <4 x i32> @test_v4i32_rot8(<4 x i32>%vec)
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{
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%rv = shufflevector <4 x i32> %vec, <4 x i32> undef,
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<4 x i32> <i32 2,i32 3,i32 0, i32 1>
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ret <4 x i32> %rv
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}
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;CHECK: test_v4i32_rot4
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define <4 x i32> @test_v4i32_rot4(<4 x i32>%vec)
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{
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%rv = shufflevector <4 x i32> %vec, <4 x i32> undef,
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<4 x i32> <i32 1,i32 2,i32 3, i32 0>
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ret <4 x i32> %rv
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}
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