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825b72b057
the latter is capable of representing either a primitive or an extended type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
340 lines
12 KiB
C++
340 lines
12 KiB
C++
//===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the SelectionDAG::LegalizeVectors method.
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//
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// The vector legalizer looks for vector operations which might need to be
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// scalarized and legalizes them. This is a separate step from Legalize because
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// scalarizing can introduce illegal types. For example, suppose we have an
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// ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
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// on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
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// operation, which introduces nodes with the illegal type i64 which must be
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// expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
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// the operation must be unrolled, which introduces nodes with the illegal
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// type i8 which must be promoted.
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//
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// This does not legalize vector manipulations like ISD::BUILD_VECTOR,
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// or operations that happen to take a vector which are custom-lowered;
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// the legalization for such operations never produces nodes
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// with illegal types, so it's okay to put off legalizing them until
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// SelectionDAG::Legalize runs.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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using namespace llvm;
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namespace {
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class VectorLegalizer {
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SelectionDAG& DAG;
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TargetLowering& TLI;
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bool Changed; // Keep track of whether anything changed
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/// LegalizedNodes - For nodes that are of legal width, and that have more
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/// than one use, this map indicates what regularized operand to use. This
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/// allows us to avoid legalizing the same thing more than once.
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DenseMap<SDValue, SDValue> LegalizedNodes;
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// Adds a node to the translation cache
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void AddLegalizedOperand(SDValue From, SDValue To) {
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LegalizedNodes.insert(std::make_pair(From, To));
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// If someone requests legalization of the new node, return itself.
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if (From != To)
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LegalizedNodes.insert(std::make_pair(To, To));
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}
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// Legalizes the given node
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SDValue LegalizeOp(SDValue Op);
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// Assuming the node is legal, "legalize" the results
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SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
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// Implements unrolling a generic vector operation, i.e. turning it into
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// scalar operations.
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SDValue UnrollVectorOp(SDValue Op);
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// Implements unrolling a VSETCC.
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SDValue UnrollVSETCC(SDValue Op);
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// Implements expansion for FNEG; falls back to UnrollVectorOp if FSUB
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// isn't legal.
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SDValue ExpandFNEG(SDValue Op);
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// Implements vector promotion; this is essentially just bitcasting the
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// operands to a different type and bitcasting the result back to the
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// original type.
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SDValue PromoteVectorOp(SDValue Op);
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public:
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bool Run();
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VectorLegalizer(SelectionDAG& dag) :
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DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
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};
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bool VectorLegalizer::Run() {
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// The legalize process is inherently a bottom-up recursive process (users
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// legalize their uses before themselves). Given infinite stack space, we
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// could just start legalizing on the root and traverse the whole graph. In
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// practice however, this causes us to run out of stack space on large basic
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// blocks. To avoid this problem, compute an ordering of the nodes where each
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// node is only legalized after all of its operands are legalized.
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DAG.AssignTopologicalOrder();
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for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
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E = prior(DAG.allnodes_end()); I != next(E); ++I)
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LegalizeOp(SDValue(I, 0));
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// Finally, it's possible the root changed. Get the new root.
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SDValue OldRoot = DAG.getRoot();
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assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
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DAG.setRoot(LegalizedNodes[OldRoot]);
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LegalizedNodes.clear();
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// Remove dead nodes now.
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DAG.RemoveDeadNodes();
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return Changed;
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}
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SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) {
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// Generic legalization: just pass the operand through.
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for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
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AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
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return Result.getValue(Op.getResNo());
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}
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SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
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// Note that LegalizeOp may be reentered even from single-use nodes, which
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// means that we always must cache transformed nodes.
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DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
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if (I != LegalizedNodes.end()) return I->second;
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SDNode* Node = Op.getNode();
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// Legalize the operands
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SmallVector<SDValue, 8> Ops;
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for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
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Ops.push_back(LegalizeOp(Node->getOperand(i)));
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SDValue Result =
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DAG.UpdateNodeOperands(Op.getValue(0), Ops.data(), Ops.size());
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bool HasVectorValue = false;
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for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
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J != E;
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++J)
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HasVectorValue |= J->isVector();
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if (!HasVectorValue)
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return TranslateLegalizeResults(Op, Result);
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EVT QueryType;
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switch (Op.getOpcode()) {
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default:
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return TranslateLegalizeResults(Op, Result);
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case ISD::ADD:
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case ISD::SUB:
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case ISD::MUL:
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case ISD::SDIV:
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case ISD::UDIV:
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case ISD::SREM:
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case ISD::UREM:
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case ISD::FADD:
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case ISD::FSUB:
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case ISD::FMUL:
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case ISD::FDIV:
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case ISD::FREM:
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case ISD::AND:
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case ISD::OR:
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case ISD::XOR:
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case ISD::SHL:
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case ISD::SRA:
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case ISD::SRL:
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case ISD::ROTL:
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case ISD::ROTR:
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case ISD::CTTZ:
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case ISD::CTLZ:
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case ISD::CTPOP:
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case ISD::SELECT:
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case ISD::SELECT_CC:
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case ISD::VSETCC:
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case ISD::ZERO_EXTEND:
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case ISD::ANY_EXTEND:
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case ISD::TRUNCATE:
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case ISD::SIGN_EXTEND:
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case ISD::FP_TO_SINT:
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case ISD::FP_TO_UINT:
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case ISD::FNEG:
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case ISD::FABS:
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case ISD::FSQRT:
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case ISD::FSIN:
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case ISD::FCOS:
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case ISD::FPOWI:
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case ISD::FPOW:
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case ISD::FLOG:
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case ISD::FLOG2:
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case ISD::FLOG10:
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case ISD::FEXP:
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case ISD::FEXP2:
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case ISD::FCEIL:
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case ISD::FTRUNC:
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case ISD::FRINT:
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case ISD::FNEARBYINT:
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case ISD::FFLOOR:
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QueryType = Node->getValueType(0);
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break;
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case ISD::SINT_TO_FP:
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case ISD::UINT_TO_FP:
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QueryType = Node->getOperand(0).getValueType();
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break;
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}
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switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) {
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case TargetLowering::Promote:
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// "Promote" the operation by bitcasting
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Result = PromoteVectorOp(Op);
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Changed = true;
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break;
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case TargetLowering::Legal: break;
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case TargetLowering::Custom: {
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SDValue Tmp1 = TLI.LowerOperation(Op, DAG);
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if (Tmp1.getNode()) {
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Result = Tmp1;
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break;
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}
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// FALL THROUGH
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}
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case TargetLowering::Expand:
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if (Node->getOpcode() == ISD::FNEG)
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Result = ExpandFNEG(Op);
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else if (Node->getOpcode() == ISD::VSETCC)
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Result = UnrollVSETCC(Op);
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else
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Result = UnrollVectorOp(Op);
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break;
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}
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// Make sure that the generated code is itself legal.
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if (Result != Op) {
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Result = LegalizeOp(Result);
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Changed = true;
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}
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// Note that LegalizeOp may be reentered even from single-use nodes, which
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// means that we always must cache transformed nodes.
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AddLegalizedOperand(Op, Result);
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return Result;
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}
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SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) {
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// Vector "promotion" is basically just bitcasting and doing the operation
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// in a different type. For example, x86 promotes ISD::AND on v2i32 to
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// v1i64.
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EVT VT = Op.getValueType();
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assert(Op.getNode()->getNumValues() == 1 &&
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"Can't promote a vector with multiple results!");
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EVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
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DebugLoc dl = Op.getDebugLoc();
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SmallVector<SDValue, 4> Operands(Op.getNumOperands());
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for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
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if (Op.getOperand(j).getValueType().isVector())
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Operands[j] = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Op.getOperand(j));
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else
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Operands[j] = Op.getOperand(j);
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}
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Op = DAG.getNode(Op.getOpcode(), dl, NVT, &Operands[0], Operands.size());
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return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Op);
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}
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SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
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if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
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SDValue Zero = DAG.getConstantFP(-0.0, Op.getValueType());
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return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
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Zero, Op.getOperand(0));
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}
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return UnrollVectorOp(Op);
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}
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SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
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EVT VT = Op.getValueType();
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unsigned NumElems = VT.getVectorNumElements();
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EVT EltVT = VT.getVectorElementType();
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SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
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EVT TmpEltVT = LHS.getValueType().getVectorElementType();
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DebugLoc dl = Op.getDebugLoc();
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SmallVector<SDValue, 8> Ops(NumElems);
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for (unsigned i = 0; i < NumElems; ++i) {
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SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
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DAG.getIntPtrConstant(i));
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SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
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DAG.getIntPtrConstant(i));
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Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT),
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LHSElem, RHSElem, CC);
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Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i],
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DAG.getConstant(APInt::getAllOnesValue
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(EltVT.getSizeInBits()), EltVT),
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DAG.getConstant(0, EltVT));
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}
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return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems);
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}
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/// UnrollVectorOp - We know that the given vector has a legal type, however
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/// the operation it performs is not legal, and the target has requested that
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/// the operation be expanded. "Unroll" the vector, splitting out the scalars
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/// and operating on each element individually.
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SDValue VectorLegalizer::UnrollVectorOp(SDValue Op) {
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EVT VT = Op.getValueType();
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assert(Op.getNode()->getNumValues() == 1 &&
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"Can't unroll a vector with multiple results!");
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unsigned NE = VT.getVectorNumElements();
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EVT EltVT = VT.getVectorElementType();
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DebugLoc dl = Op.getDebugLoc();
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SmallVector<SDValue, 8> Scalars;
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SmallVector<SDValue, 4> Operands(Op.getNumOperands());
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for (unsigned i = 0; i != NE; ++i) {
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for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
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SDValue Operand = Op.getOperand(j);
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EVT OperandVT = Operand.getValueType();
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if (OperandVT.isVector()) {
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// A vector operand; extract a single element.
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EVT OperandEltVT = OperandVT.getVectorElementType();
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Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
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OperandEltVT,
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Operand,
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DAG.getConstant(i, MVT::i32));
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} else {
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// A scalar operand; just use it as is.
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Operands[j] = Operand;
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}
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}
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switch (Op.getOpcode()) {
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default:
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Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT,
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&Operands[0], Operands.size()));
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break;
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case ISD::SHL:
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case ISD::SRA:
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case ISD::SRL:
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case ISD::ROTL:
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case ISD::ROTR:
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Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT, Operands[0],
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DAG.getShiftAmountOperand(Operands[1])));
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break;
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}
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}
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return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Scalars[0], Scalars.size());
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}
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}
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bool SelectionDAG::LegalizeVectors() {
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return VectorLegalizer(*this).Run();
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}
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