Bill Schmidt cd7a1558ed Fix PR15632: No support for ppcf128 floating-point remainder on PowerPC. ... For this we need to use a libcall. Previously LLVM didn't implement libcall support for frem, so I've added it in the usual straightforward manner. A test case from the bug report is included. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178639 91177308-0d34-0410-b5e6-96231b3b80d8		2013-04-03 13:05:44 +00:00
..
CMakeLists.txt
DAGCombiner.cpp	DAGCombiner: Merge store/loads when we have extload/truncstores	2013-04-02 15:58:51 +00:00
FastISel.cpp	[fast-isel] Add a preemptive fix for the case where we fail to materialize an	2013-03-28 23:04:47 +00:00
FunctionLoweringInfo.cpp
InstrEmitter.cpp
InstrEmitter.h
LegalizeDAG.cpp	Remove default from fully covered switch.	2013-03-08 17:03:19 +00:00
LegalizeFloatTypes.cpp	Fix PR15632: No support for ppcf128 floating-point remainder on PowerPC.	2013-04-03 13:05:44 +00:00
LegalizeIntegerTypes.cpp	Fix PR10475	2013-03-01 18:40:30 +00:00
LegalizeTypes.cpp	Move SDNode order propagation to SDNodeOrdering, which also fixes a missed	2013-03-20 14:51:01 +00:00
LegalizeTypes.h	Fix PR15632: No support for ppcf128 floating-point remainder on PowerPC.	2013-04-03 13:05:44 +00:00
LegalizeTypesGeneric.cpp
LegalizeVectorOps.cpp
LegalizeVectorTypes.cpp	SDAG: Handle scalarizing an extend of a <1 x iN> vector.	2013-03-07 05:47:54 +00:00
LLVMBuild.txt
Makefile
ResourcePriorityQueue.cpp
ScheduleDAGFast.cpp
ScheduleDAGRRList.cpp	Revert "pre-RA-sched: fix TargetOpcode usage"	2013-03-20 15:43:00 +00:00
ScheduleDAGSDNodes.cpp
ScheduleDAGSDNodes.h
ScheduleDAGVLIW.cpp
SDNodeDbgValue.h
SDNodeOrdering.h	Make variable name more explicit and eliminate redundant lookup in SDNodeOrdering	2013-03-20 23:10:59 +00:00
SelectionDAG.cpp	When computing the demanded bits of Load SDNodes, make sure that we are looking at the loaded-value operand and not the ptr result (in case of pre-inc loads).	2013-03-20 22:53:44 +00:00
SelectionDAGBuilder.cpp	Remove the type legality check from the SelectionDAGBuilder when it lowers @llvm.fmuladd to ISD::FMA nodes.	2013-03-23 08:26:53 +00:00
SelectionDAGBuilder.h
SelectionDAGDumper.cpp
SelectionDAGISel.cpp	Move SDNode order propagation to SDNodeOrdering, which also fixes a missed	2013-03-20 14:51:01 +00:00
SelectionDAGPrinter.cpp
TargetLowering.cpp
TargetSelectionDAGInfo.cpp