Craig Topper 8e121843c1 Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192566 91177308-0d34-0410-b5e6-96231b3b80d8		2013-10-14 01:42:32 +00:00
..
hex-immediates.txt
intel-syntax-32.txt
intel-syntax.txt
invalid-cmp-imm.txt
invalid-VEX-vvvv.txt
lit.local.cfg
marked-up.txt
prefixes.txt
simple-tests.txt
truncated-input.txt
x86-32.txt	Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead.	2013-10-07 07:19:47 +00:00
x86-64.txt	Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding.	2013-10-14 01:42:32 +00:00