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	Redirect the output of llc to /dev/null. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199329 91177308-0d34-0410-b5e6-96231b3b80d8
		
			
				
	
	
		
			24 lines
		
	
	
		
			1.1 KiB
		
	
	
	
		
			LLVM
		
	
	
	
	
	
			
		
		
	
	
			24 lines
		
	
	
		
			1.1 KiB
		
	
	
	
		
			LLVM
		
	
	
	
	
	
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=sse2 -mcpu=corei7 -o /dev/null
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; Revision 199135 introduced a wrong check in method
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; DAGCombiner::SimplifyVBinOp in an attempt to refactor some code
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; using the new method 'BuildVectorSDNode::isConstant' when possible.
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; 
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; However the modified code in method SimplifyVBinOp now wrongly
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; checks that the operands of a vector bin-op are both constants.
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;
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; With that wrong change, this test started failing because of a
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; 'fatal error in the backend':
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;   Cannot select: 0x2e329d0: v4i32 = BUILD_VECTOR 0x2e2ea00, 0x2e2ea00, 0x2e2ea00, 0x2e2ea00
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;       0x2e2ea00: i32 = Constant<1> [ID=4]
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;       0x2e2ea00: i32 = Constant<1> [ID=4]
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;       0x2e2ea00: i32 = Constant<1> [ID=4]
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;       0x2e2ea00: i32 = Constant<1> [ID=4]
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define <8 x i32> @reduced_test_case() {
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  %Shuff = shufflevector <8 x i32> zeroinitializer, <8 x i32> zeroinitializer, <8 x i32> <i32 1, i32 3, i32 undef, i32 7, i32 9, i32 11, i32 13, i32 15>
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  %B23 = sub <8 x i32> %Shuff, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
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  ret <8 x i32> %B23
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}
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