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f71254859e
This finishes the job started in r198756, and creates separate opcodes for
64-bit vs. 32-bit versions of the rest of the RET instructions too.
LRETL/LRETQ are interesting... I can't see any justification for their
existence in the SDM. There should be no 'LRETL' in 64-bit mode, and no
need for a REX.W prefix for LRETQ. But this is what GAS does, and my
Sandybridge CPU and an Opteron 6376 concur when tested as follows:
asm __volatile__("pushq $0x1234\nmovq $0x33,%rax\nsalq $32,%rax\norq $1f,%rax\npushq %rax\nlretl $8\n1:");
asm __volatile__("pushq $1234\npushq $0x33\npushq $1f\nlretq $8\n1:");
asm __volatile__("pushq $0x33\npushq $1f\nlretq\n1:");
asm __volatile__("pushq $0x1234\npushq $0x33\npushq $1f\nlretq $8\n1:");
cf. PR8592 and commit r118903, which added LRETQ. I only added LRETIQ to
match it.
I don't quite understand how the Intel syntax parsing for ret
instructions is working, despite r154468 allegedly fixing it. Aren't the
explicitly sized 'retw', 'retd' and 'retq' supposed to work? I have at
least made the 'lretq' work with (and indeed *require*) the 'q'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199106 91177308-0d34-0410-b5e6-96231b3b80d8
86 lines
1.9 KiB
ArmAsm
86 lines
1.9 KiB
ArmAsm
// RUN: not llvm-mc -triple x86_64-unknown-unknown --show-encoding %s 2> %t.err | FileCheck --check-prefix=64 %s
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// RUN: FileCheck --check-prefix=ERR64 < %t.err %s
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// RUN: not llvm-mc -triple i386-unknown-unknown --show-encoding %s 2> %t.err | FileCheck --check-prefix=32 %s
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// RUN: FileCheck --check-prefix=ERR32 < %t.err %s
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ret
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// 64: retq
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// 64: encoding: [0xc3]
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// 32: retl
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// 32: encoding: [0xc3]
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retw
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// 64: retw
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// 64: encoding: [0x66,0xc3]
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// 32: retw
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// 32: encoding: [0x66,0xc3]
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retl
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// ERR64: error: instruction requires: Not 64-bit mode
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// 32: retl
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// 32: encoding: [0xc3]
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retq
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// 64: retq
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// 64: encoding: [0xc3]
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// ERR32: error: instruction requires: 64-bit mode
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ret $0
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// 64: retq $0
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// 64: encoding: [0xc2,0x00,0x00]
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// 32: retl $0
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// 32: encoding: [0xc2,0x00,0x00]
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retw $0
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// 64: retw $0
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// 64: encoding: [0x66,0xc2,0x00,0x00]
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// 32: retw $0
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// 32: encoding: [0x66,0xc2,0x00,0x00]
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retl $0
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// ERR64: error: instruction requires: Not 64-bit mode
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// 32: retl $0
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// 32: encoding: [0xc2,0x00,0x00]
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retq $0
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// 64: retq $0
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// 64: encoding: [0xc2,0x00,0x00]
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// ERR32: error: instruction requires: 64-bit mode
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lret
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// 64: lretl
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// 64: encoding: [0xcb]
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// 32: lretl
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// 32: encoding: [0xcb]
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lretw
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// 64: lretw
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// 64: encoding: [0x66,0xcb]
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// 32: lretw
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// 32: encoding: [0x66,0xcb]
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lretl
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// 64: lretl
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// 64: encoding: [0xcb]
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// 32: lretl
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// 32: encoding: [0xcb]
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lretq
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// 64: lretq
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// 64: encoding: [0x48,0xcb]
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// ERR32: error: instruction requires: 64-bit mode
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lret $0
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// 64: lretl $0
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// 64: encoding: [0xca,0x00,0x00]
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// 32: lretl $0
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// 32: encoding: [0xca,0x00,0x00]
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lretw $0
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// 64: lretw $0
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// 64: encoding: [0x66,0xca,0x00,0x00]
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// 32: lretw $0
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// 32: encoding: [0x66,0xca,0x00,0x00]
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lretl $0
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// 64: lretl $0
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// 64: encoding: [0xca,0x00,0x00]
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// 32: lretl $0
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// 32: encoding: [0xca,0x00,0x00]
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lretq $0
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// 64: lretq $0
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// 64: encoding: [0x48,0xca,0x00,0x00]
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// ERR32: error: instruction requires: 64-bit mode
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