mirror of
https://github.com/c64scene-ar/llvm-6502.git
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9bcdcd17c7
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13956 91177308-0d34-0410-b5e6-96231b3b80d8
364 lines
15 KiB
C++
364 lines
15 KiB
C++
//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the virtual register map. It also implements
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// the eliminateVirtRegs() function that given a virtual register map
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// and a machine function it eliminates all virtual references by
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// replacing them with physical register references and adds spill
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// code as necessary.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "VirtRegMap.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "Support/CommandLine.h"
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#include "Support/Debug.h"
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#include "Support/DenseMap.h"
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#include "Support/Statistic.h"
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#include "Support/STLExtras.h"
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#include <iostream>
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using namespace llvm;
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namespace {
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Statistic<> numSpills("spiller", "Number of register spills");
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Statistic<> numStores("spiller", "Number of stores added");
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Statistic<> numLoads ("spiller", "Number of loads added");
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enum SpillerName { simple, local };
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cl::opt<SpillerName>
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SpillerOpt("spiller",
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cl::desc("Spiller to use: (default: local)"),
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cl::Prefix,
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cl::values(clEnumVal(simple, " simple spiller"),
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clEnumVal(local, " local spiller"),
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0),
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cl::init(local));
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}
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int VirtRegMap::assignVirt2StackSlot(unsigned virtReg)
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{
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assert(MRegisterInfo::isVirtualRegister(virtReg));
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assert(v2ssMap_[virtReg] == NO_STACK_SLOT &&
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"attempt to assign stack slot to already spilled register");
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const TargetRegisterClass* rc =
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mf_->getSSARegMap()->getRegClass(virtReg);
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int frameIndex = mf_->getFrameInfo()->CreateStackObject(rc);
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v2ssMap_[virtReg] = frameIndex;
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++numSpills;
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return frameIndex;
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}
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void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex)
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{
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assert(MRegisterInfo::isVirtualRegister(virtReg));
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assert(v2ssMap_[virtReg] == NO_STACK_SLOT &&
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"attempt to assign stack slot to already spilled register");
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v2ssMap_[virtReg] = frameIndex;
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}
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void VirtRegMap::virtFolded(unsigned virtReg,
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MachineInstr* oldMI,
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MachineInstr* newMI)
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{
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// move previous memory references folded to new instruction
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MI2VirtMap::iterator i, e;
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std::vector<MI2VirtMap::mapped_type> regs;
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for (tie(i, e) = mi2vMap_.equal_range(oldMI); i != e; ) {
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regs.push_back(i->second);
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mi2vMap_.erase(i++);
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}
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for (unsigned i = 0, e = regs.size(); i != e; ++i)
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mi2vMap_.insert(std::make_pair(newMI, i));
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// add new memory reference
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mi2vMap_.insert(std::make_pair(newMI, virtReg));
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}
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std::ostream& llvm::operator<<(std::ostream& os, const VirtRegMap& vrm)
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{
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const MRegisterInfo* mri = vrm.mf_->getTarget().getRegisterInfo();
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std::cerr << "********** REGISTER MAP **********\n";
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for (unsigned i = MRegisterInfo::FirstVirtualRegister,
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e = vrm.mf_->getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
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if (vrm.v2pMap_[i] != VirtRegMap::NO_PHYS_REG)
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std::cerr << "[reg" << i << " -> "
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<< mri->getName(vrm.v2pMap_[i]) << "]\n";
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}
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for (unsigned i = MRegisterInfo::FirstVirtualRegister,
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e = vrm.mf_->getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
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if (vrm.v2ssMap_[i] != VirtRegMap::NO_STACK_SLOT)
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std::cerr << "[reg" << i << " -> fi#"
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<< vrm.v2ssMap_[i] << "]\n";
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}
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return std::cerr << '\n';
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}
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Spiller::~Spiller()
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{
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}
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namespace {
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class SimpleSpiller : public Spiller {
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public:
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bool runOnMachineFunction(MachineFunction& mf, const VirtRegMap& vrm) {
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DEBUG(std::cerr << "********** REWRITE MACHINE CODE **********\n");
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DEBUG(std::cerr << "********** Function: "
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<< mf.getFunction()->getName() << '\n');
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const TargetMachine& tm = mf.getTarget();
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const MRegisterInfo& mri = *tm.getRegisterInfo();
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typedef DenseMap<bool, VirtReg2IndexFunctor> Loaded;
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Loaded loaded;
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for (MachineFunction::iterator mbbi = mf.begin(),
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mbbe = mf.end(); mbbi != mbbe; ++mbbi) {
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DEBUG(std::cerr << mbbi->getBasicBlock()->getName() << ":\n");
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for (MachineBasicBlock::iterator mii = mbbi->begin(),
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mie = mbbi->end(); mii != mie; ++mii) {
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loaded.grow(mf.getSSARegMap()->getLastVirtReg());
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for (unsigned i = 0,e = mii->getNumOperands(); i != e; ++i){
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MachineOperand& mop = mii->getOperand(i);
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if (mop.isRegister() && mop.getReg() &&
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MRegisterInfo::isVirtualRegister(mop.getReg())) {
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unsigned virtReg = mop.getReg();
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unsigned physReg = vrm.getPhys(virtReg);
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if (mop.isUse() &&
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vrm.hasStackSlot(mop.getReg()) &&
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!loaded[virtReg]) {
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mri.loadRegFromStackSlot(
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*mbbi,
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mii,
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physReg,
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vrm.getStackSlot(virtReg),
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mf.getSSARegMap()->getRegClass(virtReg));
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loaded[virtReg] = true;
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DEBUG(std::cerr << '\t';
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prior(mii)->print(std::cerr, tm));
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++numLoads;
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}
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if (mop.isDef() &&
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vrm.hasStackSlot(mop.getReg())) {
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mri.storeRegToStackSlot(
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*mbbi,
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next(mii),
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physReg,
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vrm.getStackSlot(virtReg),
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mf.getSSARegMap()->getRegClass(virtReg));
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++numStores;
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}
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mii->SetMachineOperandReg(i, physReg);
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}
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}
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DEBUG(std::cerr << '\t'; mii->print(std::cerr, tm));
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loaded.clear();
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}
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}
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return true;
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}
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};
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class LocalSpiller : public Spiller {
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typedef std::vector<unsigned> Phys2VirtMap;
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typedef std::vector<bool> PhysFlag;
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typedef DenseMap<MachineInstr*, VirtReg2IndexFunctor> Virt2MI;
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MachineFunction* mf_;
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const TargetMachine* tm_;
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const TargetInstrInfo* tii_;
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const MRegisterInfo* mri_;
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const VirtRegMap* vrm_;
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Phys2VirtMap p2vMap_;
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PhysFlag dirty_;
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Virt2MI lastDef_;
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public:
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bool runOnMachineFunction(MachineFunction& mf, const VirtRegMap& vrm) {
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mf_ = &mf;
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tm_ = &mf_->getTarget();
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tii_ = tm_->getInstrInfo();
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mri_ = tm_->getRegisterInfo();
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vrm_ = &vrm;
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p2vMap_.assign(mri_->getNumRegs(), 0);
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dirty_.assign(mri_->getNumRegs(), false);
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DEBUG(std::cerr << "********** REWRITE MACHINE CODE **********\n");
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DEBUG(std::cerr << "********** Function: "
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<< mf_->getFunction()->getName() << '\n');
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for (MachineFunction::iterator mbbi = mf_->begin(),
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mbbe = mf_->end(); mbbi != mbbe; ++mbbi) {
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lastDef_.grow(mf_->getSSARegMap()->getLastVirtReg());
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DEBUG(std::cerr << mbbi->getBasicBlock()->getName() << ":\n");
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eliminateVirtRegsInMbb(*mbbi);
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// clear map, dirty flag and last ref
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p2vMap_.assign(p2vMap_.size(), 0);
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dirty_.assign(dirty_.size(), false);
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lastDef_.clear();
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}
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return true;
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}
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private:
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void vacateJustPhysReg(MachineBasicBlock& mbb,
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MachineBasicBlock::iterator mii,
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unsigned physReg) {
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unsigned virtReg = p2vMap_[physReg];
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if (dirty_[physReg] && vrm_->hasStackSlot(virtReg)) {
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assert(lastDef_[virtReg] && "virtual register is mapped "
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"to a register and but was not defined!");
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MachineBasicBlock::iterator lastDef = lastDef_[virtReg];
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MachineBasicBlock::iterator nextLastRef = next(lastDef);
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mri_->storeRegToStackSlot(*lastDef->getParent(),
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nextLastRef,
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physReg,
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vrm_->getStackSlot(virtReg),
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mri_->getRegClass(physReg));
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++numStores;
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DEBUG(std::cerr << "added: ";
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prior(nextLastRef)->print(std::cerr, *tm_);
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std::cerr << "after: ";
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lastDef->print(std::cerr, *tm_));
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lastDef_[virtReg] = 0;
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}
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p2vMap_[physReg] = 0;
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dirty_[physReg] = false;
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}
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void vacatePhysReg(MachineBasicBlock& mbb,
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MachineBasicBlock::iterator mii,
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unsigned physReg) {
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vacateJustPhysReg(mbb, mii, physReg);
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for (const unsigned* as = mri_->getAliasSet(physReg); *as; ++as)
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vacateJustPhysReg(mbb, mii, *as);
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}
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void handleUse(MachineBasicBlock& mbb,
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MachineBasicBlock::iterator mii,
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unsigned virtReg,
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unsigned physReg) {
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// check if we are replacing a previous mapping
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if (p2vMap_[physReg] != virtReg) {
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vacatePhysReg(mbb, mii, physReg);
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p2vMap_[physReg] = virtReg;
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// load if necessary
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if (vrm_->hasStackSlot(virtReg)) {
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mri_->loadRegFromStackSlot(mbb, mii, physReg,
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vrm_->getStackSlot(virtReg),
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mri_->getRegClass(physReg));
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++numLoads;
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DEBUG(std::cerr << "added: ";
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prior(mii)->print(std::cerr, *tm_));
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lastDef_[virtReg] = mii;
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}
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}
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}
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void handleDef(MachineBasicBlock& mbb,
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MachineBasicBlock::iterator mii,
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unsigned virtReg,
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unsigned physReg) {
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// check if we are replacing a previous mapping
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if (p2vMap_[physReg] != virtReg)
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vacatePhysReg(mbb, mii, physReg);
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p2vMap_[physReg] = virtReg;
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dirty_[physReg] = true;
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lastDef_[virtReg] = mii;
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}
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void eliminateVirtRegsInMbb(MachineBasicBlock& mbb) {
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for (MachineBasicBlock::iterator mii = mbb.begin(),
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mie = mbb.end(); mii != mie; ++mii) {
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// if we have references to memory operands make sure
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// we clear all physical registers that may contain
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// the value of the spilled virtual register
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VirtRegMap::MI2VirtMap::const_iterator i, e;
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for (tie(i, e) = vrm_->getFoldedVirts(mii); i != e; ++i) {
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if (vrm_->hasPhys(i->second))
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vacateJustPhysReg(mbb, mii, vrm_->getPhys(i->second));
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}
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// rewrite all used operands
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for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
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MachineOperand& op = mii->getOperand(i);
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if (op.isRegister() && op.getReg() && op.isUse() &&
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MRegisterInfo::isVirtualRegister(op.getReg())) {
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unsigned virtReg = op.getReg();
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unsigned physReg = vrm_->getPhys(virtReg);
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handleUse(mbb, mii, virtReg, physReg);
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mii->SetMachineOperandReg(i, physReg);
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// mark as dirty if this is def&use
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if (op.isDef()) {
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dirty_[physReg] = true;
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lastDef_[virtReg] = mii;
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}
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}
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}
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// spill implicit physical register defs
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const TargetInstrDescriptor& tid = tii_->get(mii->getOpcode());
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for (const unsigned* id = tid.ImplicitDefs; *id; ++id)
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vacatePhysReg(mbb, mii, *id);
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// spill explicit physical register defs
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for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
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MachineOperand& op = mii->getOperand(i);
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if (op.isRegister() && op.getReg() && !op.isUse() &&
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MRegisterInfo::isPhysicalRegister(op.getReg()))
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vacatePhysReg(mbb, mii, op.getReg());
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}
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// rewrite def operands (def&use was handled with the
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// uses so don't check for those here)
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for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
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MachineOperand& op = mii->getOperand(i);
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if (op.isRegister() && op.getReg() && !op.isUse())
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if (MRegisterInfo::isPhysicalRegister(op.getReg()))
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vacatePhysReg(mbb, mii, op.getReg());
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else {
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unsigned physReg = vrm_->getPhys(op.getReg());
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handleDef(mbb, mii, op.getReg(), physReg);
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mii->SetMachineOperandReg(i, physReg);
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}
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}
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DEBUG(std::cerr << '\t'; mii->print(std::cerr, *tm_));
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}
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for (unsigned i = 1, e = p2vMap_.size(); i != e; ++i)
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vacateJustPhysReg(mbb, mbb.getFirstTerminator(), i);
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}
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};
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}
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llvm::Spiller* llvm::createSpiller()
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{
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switch (SpillerOpt) {
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default:
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std::cerr << "no spiller selected";
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abort();
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case local:
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return new LocalSpiller();
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case simple:
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return new SimpleSpiller();
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}
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}
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