Tim Northover cf3e4cb29a ARM: allow cortex-m0 to use hint instructions ... The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have been ported across to the v6M architecture. Fortunately, v6M seems to sit nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it fairly easily. rdar://problem/15144406 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192097 91177308-0d34-0410-b5e6-96231b3b80d8		2013-10-07 11:10:47 +00:00
..
AArch64	Implement aarch64 neon instruction set AdvSIMD (Across).	2013-10-05 08:22:10 +00:00
ARM	ARM: allow cortex-m0 to use hint instructions	2013-10-07 11:10:47 +00:00
AsmParser	MCParser/Debug info: Accept line number 0 as a legitimate value, since	2013-09-26 23:37:11 +00:00
COFF	COFF: Ensure that objects produced by LLVM link with /safeseh	2013-09-17 23:18:05 +00:00
Disassembler	Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead.	2013-10-07 07:19:47 +00:00
ELF	Implements parsing and emitting of .cfi_window_save in MC.	2013-09-26 14:49:40 +00:00
MachO	Add test I forgot to git add in r191824.	2013-10-02 14:49:41 +00:00
Markup
Mips	Remove some really nasty uses of hasRawTextSupport.	2013-10-05 16:42:21 +00:00
PowerPC	PPC: Allow partial fills in writeNopData()	2013-09-26 09:18:48 +00:00
SystemZ	[SystemZ] Add comparisons of high words and memory	2013-10-01 15:00:44 +00:00
X86	Teach X86 asm parser that VMOVAPSrr and other VEX-encoded register to register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not.	2013-10-07 05:42:48 +00:00