mirror of
https://github.com/c64scene-ar/llvm-6502.git
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d0fde30ce8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9903 91177308-0d34-0410-b5e6-96231b3b80d8
231 lines
8.5 KiB
C++
231 lines
8.5 KiB
C++
//===- CodeEmitterGen.cpp - Code Emitter Generator ------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// FIXME: Document.
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//
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//===----------------------------------------------------------------------===//
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#include "CodeEmitterGen.h"
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#include "Record.h"
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#include "Support/Debug.h"
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namespace llvm {
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void CodeEmitterGen::run(std::ostream &o) {
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std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
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EmitSourceFileHeader("Machine Code Emitter", o);
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std::string Namespace = "V9::";
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std::string ClassName = "SparcV9CodeEmitter::";
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//const std::string &Namespace = Inst->getValue("Namespace")->getName();
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o << "unsigned " << ClassName
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<< "getBinaryCodeForInstr(MachineInstr &MI) {\n"
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<< " unsigned Value = 0;\n"
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<< " DEBUG(std::cerr << MI);\n"
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<< " switch (MI.getOpcode()) {\n";
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for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
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I != E; ++I) {
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Record *R = *I;
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o << " case " << Namespace << R->getName() << ": {\n"
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<< " DEBUG(std::cerr << \"Emitting " << R->getName() << "\\n\");\n";
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BitsInit *BI = R->getValueAsBitsInit("Inst");
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unsigned Value = 0;
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const std::vector<RecordVal> &Vals = R->getValues();
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DEBUG(o << " // prefilling: ");
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// Start by filling in fixed values...
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for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) {
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if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(e-i-1))) {
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Value |= B->getValue() << (e-i-1);
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DEBUG(o << B->getValue());
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} else {
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DEBUG(o << "0");
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}
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}
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DEBUG(o << "\n");
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DEBUG(o << " // " << *R->getValue("Inst") << "\n");
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o << " Value = " << Value << "U;\n\n";
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// Loop over all of the fields in the instruction determining which are the
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// operands to the instruction.
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//
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unsigned op = 0;
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std::map<std::string, unsigned> OpOrder;
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std::map<std::string, bool> OpContinuous;
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for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
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if (!Vals[i].getPrefix() && !Vals[i].getValue()->isComplete()) {
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// Is the operand continuous? If so, we can just mask and OR it in
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// instead of doing it bit-by-bit, saving a lot in runtime cost.
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const BitsInit *InstInit = BI;
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int beginBitInVar = -1, endBitInVar = -1;
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int beginBitInInst = -1, endBitInInst = -1;
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bool continuous = true;
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for (int bit = InstInit->getNumBits()-1; bit >= 0; --bit) {
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if (VarBitInit *VBI =
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dynamic_cast<VarBitInit*>(InstInit->getBit(bit))) {
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TypedInit *TI = VBI->getVariable();
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if (VarInit *VI = dynamic_cast<VarInit*>(TI)) {
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// only process the current variable
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if (VI->getName() != Vals[i].getName())
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continue;
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if (beginBitInVar == -1)
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beginBitInVar = VBI->getBitNum();
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if (endBitInVar == -1)
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endBitInVar = VBI->getBitNum();
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else {
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if (endBitInVar == (int)VBI->getBitNum() + 1)
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endBitInVar = VBI->getBitNum();
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else {
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continuous = false;
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break;
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}
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}
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if (beginBitInInst == -1)
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beginBitInInst = bit;
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if (endBitInInst == -1)
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endBitInInst = bit;
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else {
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if (endBitInInst == bit + 1)
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endBitInInst = bit;
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else {
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continuous = false;
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break;
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}
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}
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// maintain same distance between bits in field and bits in
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// instruction. if the relative distances stay the same
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// throughout,
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if (beginBitInVar - (int)VBI->getBitNum() !=
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beginBitInInst - bit) {
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continuous = false;
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break;
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}
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}
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}
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}
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// If we have found no bit in "Inst" which comes from this field, then
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// this is not an operand!!
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if (beginBitInInst != -1) {
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o << " // op" << op << ": " << Vals[i].getName() << "\n"
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<< " int64_t op" << op
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<<" = getMachineOpValue(MI, MI.getOperand("<<op<<"));\n";
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//<< " MachineOperand &op" << op <<" = MI.getOperand("<<op<<");\n";
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OpOrder[Vals[i].getName()] = op++;
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DEBUG(o << " // Var: begin = " << beginBitInVar
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<< ", end = " << endBitInVar
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<< "; Inst: begin = " << beginBitInInst
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<< ", end = " << endBitInInst << "\n");
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if (continuous) {
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DEBUG(o << " // continuous: op" << OpOrder[Vals[i].getName()]
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<< "\n");
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// Mask off the right bits
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// Low mask (ie. shift, if necessary)
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assert(endBitInVar >= 0 && "Negative shift amount in masking!");
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if (endBitInVar != 0) {
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o << " op" << OpOrder[Vals[i].getName()]
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<< " >>= " << endBitInVar << ";\n";
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beginBitInVar -= endBitInVar;
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endBitInVar = 0;
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}
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// High mask
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o << " op" << OpOrder[Vals[i].getName()]
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<< " &= (1<<" << beginBitInVar+1 << ") - 1;\n";
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// Shift the value to the correct place (according to place in inst)
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assert(endBitInInst >= 0 && "Negative shift amount in inst position!");
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if (endBitInInst != 0)
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o << " op" << OpOrder[Vals[i].getName()]
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<< " <<= " << endBitInInst << ";\n";
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// Just OR in the result
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o << " Value |= op" << OpOrder[Vals[i].getName()] << ";\n";
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}
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// otherwise, will be taken care of in the loop below using this
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// value:
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OpContinuous[Vals[i].getName()] = continuous;
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}
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}
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}
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for (unsigned f = 0, e = Vals.size(); f != e; ++f) {
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if (Vals[f].getPrefix()) {
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BitsInit *FieldInitializer = (BitsInit*)Vals[f].getValue();
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// Scan through the field looking for bit initializers of the current
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// variable...
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for (int i = FieldInitializer->getNumBits()-1; i >= 0; --i) {
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if (BitInit *BI = dynamic_cast<BitInit*>(FieldInitializer->getBit(i)))
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{
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DEBUG(o << " // bit init: f: " << f << ", i: " << i << "\n");
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} else if (UnsetInit *UI =
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dynamic_cast<UnsetInit*>(FieldInitializer->getBit(i))) {
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DEBUG(o << " // unset init: f: " << f << ", i: " << i << "\n");
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} else if (VarBitInit *VBI =
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dynamic_cast<VarBitInit*>(FieldInitializer->getBit(i))) {
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TypedInit *TI = VBI->getVariable();
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if (VarInit *VI = dynamic_cast<VarInit*>(TI)) {
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// If the bits of the field are laid out consecutively in the
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// instruction, then instead of separately ORing in bits, just
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// mask and shift the entire field for efficiency.
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if (OpContinuous[VI->getName()]) {
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// already taken care of in the loop above, thus there is no
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// need to individually OR in the bits
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// for debugging, output the regular version anyway, commented
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DEBUG(o << " // Value |= getValueBit(op"
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<< OpOrder[VI->getName()] << ", " << VBI->getBitNum()
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<< ")" << " << " << i << ";\n");
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} else {
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o << " Value |= getValueBit(op" << OpOrder[VI->getName()]
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<< ", " << VBI->getBitNum()
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<< ")" << " << " << i << ";\n";
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}
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} else if (FieldInit *FI = dynamic_cast<FieldInit*>(TI)) {
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// FIXME: implement this!
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o << "FIELD INIT not implemented yet!\n";
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} else {
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o << "Error: UNIMPLEMENTED\n";
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}
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}
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}
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}
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}
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o << " break;\n"
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<< " }\n";
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}
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o << " default:\n"
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<< " std::cerr << \"Not supported instr: \" << MI << \"\\n\";\n"
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<< " abort();\n"
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<< " }\n"
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<< " return Value;\n"
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<< "}\n";
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EmitSourceFileTail(o);
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}
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} // End llvm namespace
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