Vincent Lejeune f3d6e32c09 R600: Add a pass that merge Vector Register ... Previously commited @183279 but tests were failing, reverted @183286 It was broken because @183336 was missing, now it's there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183343 91177308-0d34-0410-b5e6-96231b3b80d8		2013-06-05 21:38:04 +00:00
..
AArch64	Change how we iterate over relocations on ELF.	2013-05-30 03:05:14 +00:00
ARM	Cortex-R5 can issue Thumb2 integer division instructions.	2013-06-04 22:52:09 +00:00
CPP
Generic	Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.	2013-05-21 14:37:16 +00:00
Hexagon
Inputs
MBlaze
Mips	[mips] brcond + setgt/setugt instruction selection patterns.	2013-06-05 19:49:55 +00:00
MSP430
NVPTX	[NVPTX] Re-enable support for virtual registers in the final output	2013-05-31 12:14:49 +00:00
PowerPC	Change how we iterate over relocations on ELF.	2013-05-30 03:05:14 +00:00
R600	R600: Add a pass that merge Vector Register	2013-06-05 21:38:04 +00:00
SI
SPARC	Sparc: Add support for indirect branch and blockaddress in Sparc backend.	2013-06-03 05:58:33 +00:00
SystemZ	[SystemZ] Don't use LOAD and STORE REVERSED for volatile accesses	2013-05-31 13:25:22 +00:00
Thumb
Thumb2	Cortex-R5 can issue Thumb2 integer division instructions.	2013-06-04 22:52:09 +00:00
X86	[PATCH] Fix VGATHER* operand constraints	2013-06-05 18:12:26 +00:00
XCore