llvm-6502/lib/CodeGen
2007-03-27 00:53:36 +00:00
..
SelectionDAG SDISel does not preserve all, it changes CFG and other info. 2007-03-27 00:53:36 +00:00
AsmPrinter.cpp
BranchFolding.cpp maintain LiveIn when splitting blocks (register scavenging needs it) 2007-03-20 21:35:06 +00:00
DwarfWriter.cpp Cleanup: make SetCounter an instance variable 2007-03-07 08:25:02 +00:00
ELFWriter.cpp
ELFWriter.h
IntrinsicLowering.cpp
LiveInterval.cpp
LiveIntervalAnalysis.cpp Fix for PR1266. Don't mark a two address operand IsKill. 2007-03-26 22:40:42 +00:00
LiveVariables.cpp Track the BB's where each virtual register is used. 2007-03-17 09:29:54 +00:00
LLVMTargetMachine.cpp Now LoopStrengthReduce is a LoopPass. 2007-03-06 21:14:09 +00:00
MachineBasicBlock.cpp Print preds / succs BB numbers. 2007-03-09 08:29:08 +00:00
MachineFunction.cpp
MachineInstr.cpp Change findRegisterUseOperand() to return operand index instead. 2007-03-26 22:37:45 +00:00
MachineModuleInfo.cpp
MachinePassRegistry.cpp
MachOWriter.cpp
MachOWriter.h
Makefile
Passes.cpp
PHIElimination.cpp Keep UsedBlocks info accurate. 2007-03-18 09:02:31 +00:00
PhysRegTracker.h
PrologEpilogInserter.cpp
README.txt Potential spiller improvement. 2007-03-20 22:22:38 +00:00
RegAllocLinearScan.cpp First cut trivial re-materialization support. 2007-03-20 08:13:50 +00:00
RegAllocLocal.cpp
RegAllocSimple.cpp
RegisterScavenging.cpp Fix reversed logic in getRegsUsed. Rename RegStates to RegsAvailable to 2007-03-26 22:23:54 +00:00
TwoAddressInstructionPass.cpp Keep UsedBlocks info accurate. 2007-03-18 09:02:31 +00:00
UnreachableBlockElim.cpp
VirtRegMap.cpp Don't call getOperandConstraint() if operand index is greater than 2007-03-27 00:48:28 +00:00
VirtRegMap.h First cut trivial re-materialization support. 2007-03-20 08:13:50 +00:00

Common register allocation / spilling problem:

	mul lr, r4, lr
	str lr, [sp, #+52]
	ldr lr, [r1, #+32]
	sxth r3, r3
	ldr r4, [sp, #+52]
	mla r4, r3, lr, r4

can be:

	mul lr, r4, lr
        mov r4, lr
	str lr, [sp, #+52]
	ldr lr, [r1, #+32]
	sxth r3, r3
	mla r4, r3, lr, r4

and then "merge" mul and mov:

	mul r4, r4, lr
	str lr, [sp, #+52]
	ldr lr, [r1, #+32]
	sxth r3, r3
	mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.