mirror of
https://github.com/c64scene-ar/llvm-6502.git
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dae2a20a56
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178667 91177308-0d34-0410-b5e6-96231b3b80d8
428 lines
12 KiB
C++
428 lines
12 KiB
C++
//===-- R600MachineScheduler.cpp - R600 Scheduler Interface -*- C++ -*-----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief R600 Machine Scheduler interface
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// TODO: Scheduling is optimised for VLIW4 arch, modify it to support TRANS slot
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "misched"
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#include "R600MachineScheduler.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/Pass.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/raw_ostream.h"
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#include <set>
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using namespace llvm;
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void R600SchedStrategy::initialize(ScheduleDAGMI *dag) {
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DAG = dag;
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TII = static_cast<const R600InstrInfo*>(DAG->TII);
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TRI = static_cast<const R600RegisterInfo*>(DAG->TRI);
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MRI = &DAG->MRI;
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Available[IDAlu]->clear();
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Available[IDFetch]->clear();
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Available[IDOther]->clear();
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CurInstKind = IDOther;
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CurEmitted = 0;
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OccupedSlotsMask = 15;
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InstKindLimit[IDAlu] = TII->getMaxAlusPerClause();
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const AMDGPUSubtarget &ST = DAG->TM.getSubtarget<AMDGPUSubtarget>();
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if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD5XXX) {
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InstKindLimit[IDFetch] = 7; // 8 minus 1 for security
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} else {
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InstKindLimit[IDFetch] = 15; // 16 minus 1 for security
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}
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}
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void R600SchedStrategy::MoveUnits(ReadyQueue *QSrc, ReadyQueue *QDst)
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{
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if (QSrc->empty())
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return;
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for (ReadyQueue::iterator I = QSrc->begin(),
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E = QSrc->end(); I != E; ++I) {
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(*I)->NodeQueueId &= ~QSrc->getID();
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QDst->push(*I);
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}
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QSrc->clear();
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}
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SUnit* R600SchedStrategy::pickNode(bool &IsTopNode) {
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SUnit *SU = 0;
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IsTopNode = true;
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NextInstKind = IDOther;
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// check if we might want to switch current clause type
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bool AllowSwitchToAlu = (CurInstKind == IDOther) ||
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(CurEmitted > InstKindLimit[CurInstKind]) ||
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(Available[CurInstKind]->empty());
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bool AllowSwitchFromAlu = (CurEmitted > InstKindLimit[CurInstKind]) &&
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(!Available[IDFetch]->empty() || !Available[IDOther]->empty());
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if ((AllowSwitchToAlu && CurInstKind != IDAlu) ||
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(!AllowSwitchFromAlu && CurInstKind == IDAlu)) {
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// try to pick ALU
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SU = pickAlu();
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if (SU) {
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if (CurEmitted > InstKindLimit[IDAlu])
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CurEmitted = 0;
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NextInstKind = IDAlu;
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}
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}
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if (!SU) {
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// try to pick FETCH
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SU = pickOther(IDFetch);
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if (SU)
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NextInstKind = IDFetch;
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}
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// try to pick other
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if (!SU) {
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SU = pickOther(IDOther);
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if (SU)
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NextInstKind = IDOther;
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}
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DEBUG(
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if (SU) {
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dbgs() << "picked node: ";
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SU->dump(DAG);
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} else {
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dbgs() << "NO NODE ";
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for (int i = 0; i < IDLast; ++i) {
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Available[i]->dump();
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Pending[i]->dump();
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}
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for (unsigned i = 0; i < DAG->SUnits.size(); i++) {
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const SUnit &S = DAG->SUnits[i];
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if (!S.isScheduled)
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S.dump(DAG);
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}
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}
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);
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return SU;
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}
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void R600SchedStrategy::schedNode(SUnit *SU, bool IsTopNode) {
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DEBUG(dbgs() << "scheduled: ");
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DEBUG(SU->dump(DAG));
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if (NextInstKind != CurInstKind) {
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DEBUG(dbgs() << "Instruction Type Switch\n");
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if (NextInstKind != IDAlu)
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OccupedSlotsMask = 15;
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CurEmitted = 0;
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CurInstKind = NextInstKind;
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}
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if (CurInstKind == IDAlu) {
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switch (getAluKind(SU)) {
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case AluT_XYZW:
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CurEmitted += 4;
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break;
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case AluDiscarded:
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break;
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default: {
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++CurEmitted;
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for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(),
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E = SU->getInstr()->operands_end(); It != E; ++It) {
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MachineOperand &MO = *It;
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if (MO.isReg() && MO.getReg() == AMDGPU::ALU_LITERAL_X)
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++CurEmitted;
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}
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}
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}
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} else {
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++CurEmitted;
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}
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DEBUG(dbgs() << CurEmitted << " Instructions Emitted in this clause\n");
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if (CurInstKind != IDFetch) {
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MoveUnits(Pending[IDFetch], Available[IDFetch]);
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}
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MoveUnits(Pending[IDOther], Available[IDOther]);
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}
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void R600SchedStrategy::releaseTopNode(SUnit *SU) {
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int IK = getInstKind(SU);
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DEBUG(dbgs() << IK << " <= ");
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DEBUG(SU->dump(DAG));
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Pending[IK]->push(SU);
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}
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void R600SchedStrategy::releaseBottomNode(SUnit *SU) {
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}
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bool R600SchedStrategy::regBelongsToClass(unsigned Reg,
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const TargetRegisterClass *RC) const {
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if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
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return RC->contains(Reg);
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} else {
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return MRI->getRegClass(Reg) == RC;
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}
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}
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R600SchedStrategy::AluKind R600SchedStrategy::getAluKind(SUnit *SU) const {
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MachineInstr *MI = SU->getInstr();
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switch (MI->getOpcode()) {
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case AMDGPU::INTERP_PAIR_XY:
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case AMDGPU::INTERP_PAIR_ZW:
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case AMDGPU::INTERP_VEC_LOAD:
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return AluT_XYZW;
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case AMDGPU::COPY:
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if (TargetRegisterInfo::isPhysicalRegister(MI->getOperand(1).getReg())) {
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// %vregX = COPY Tn_X is likely to be discarded in favor of an
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// assignement of Tn_X to %vregX, don't considers it in scheduling
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return AluDiscarded;
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}
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else if (MI->getOperand(1).isUndef()) {
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// MI will become a KILL, don't considers it in scheduling
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return AluDiscarded;
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}
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default:
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break;
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}
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// Does the instruction take a whole IG ?
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if(TII->isVector(*MI) ||
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TII->isCubeOp(MI->getOpcode()) ||
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TII->isReductionOp(MI->getOpcode()))
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return AluT_XYZW;
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// Is the result already assigned to a channel ?
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unsigned DestSubReg = MI->getOperand(0).getSubReg();
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switch (DestSubReg) {
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case AMDGPU::sub0:
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return AluT_X;
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case AMDGPU::sub1:
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return AluT_Y;
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case AMDGPU::sub2:
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return AluT_Z;
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case AMDGPU::sub3:
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return AluT_W;
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default:
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break;
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}
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// Is the result already member of a X/Y/Z/W class ?
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unsigned DestReg = MI->getOperand(0).getReg();
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if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_XRegClass) ||
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regBelongsToClass(DestReg, &AMDGPU::R600_AddrRegClass))
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return AluT_X;
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if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_YRegClass))
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return AluT_Y;
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if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass))
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return AluT_Z;
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if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_WRegClass))
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return AluT_W;
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if (regBelongsToClass(DestReg, &AMDGPU::R600_Reg128RegClass))
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return AluT_XYZW;
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return AluAny;
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}
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int R600SchedStrategy::getInstKind(SUnit* SU) {
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int Opcode = SU->getInstr()->getOpcode();
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if (TII->isALUInstr(Opcode)) {
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return IDAlu;
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}
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switch (Opcode) {
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case AMDGPU::COPY:
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case AMDGPU::CONST_COPY:
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case AMDGPU::INTERP_PAIR_XY:
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case AMDGPU::INTERP_PAIR_ZW:
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case AMDGPU::INTERP_VEC_LOAD:
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case AMDGPU::DOT4_eg_pseudo:
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case AMDGPU::DOT4_r600_pseudo:
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return IDAlu;
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case AMDGPU::TEX_VTX_CONSTBUF:
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case AMDGPU::TEX_VTX_TEXBUF:
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case AMDGPU::TEX_LD:
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case AMDGPU::TEX_GET_TEXTURE_RESINFO:
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case AMDGPU::TEX_GET_GRADIENTS_H:
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case AMDGPU::TEX_GET_GRADIENTS_V:
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case AMDGPU::TEX_SET_GRADIENTS_H:
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case AMDGPU::TEX_SET_GRADIENTS_V:
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case AMDGPU::TEX_SAMPLE:
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case AMDGPU::TEX_SAMPLE_C:
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case AMDGPU::TEX_SAMPLE_L:
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case AMDGPU::TEX_SAMPLE_C_L:
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case AMDGPU::TEX_SAMPLE_LB:
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case AMDGPU::TEX_SAMPLE_C_LB:
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case AMDGPU::TEX_SAMPLE_G:
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case AMDGPU::TEX_SAMPLE_C_G:
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case AMDGPU::TXD:
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case AMDGPU::TXD_SHADOW:
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return IDFetch;
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default:
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DEBUG(
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dbgs() << "other inst: ";
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SU->dump(DAG);
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);
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return IDOther;
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}
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}
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SUnit *R600SchedStrategy::PopInst(std::multiset<SUnit *, CompareSUnit> &Q) {
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if (Q.empty())
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return NULL;
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for (std::set<SUnit *, CompareSUnit>::iterator It = Q.begin(), E = Q.end();
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It != E; ++It) {
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SUnit *SU = *It;
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InstructionsGroupCandidate.push_back(SU->getInstr());
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if (TII->canBundle(InstructionsGroupCandidate)) {
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InstructionsGroupCandidate.pop_back();
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Q.erase(It);
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return SU;
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} else {
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InstructionsGroupCandidate.pop_back();
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}
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}
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return NULL;
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}
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void R600SchedStrategy::LoadAlu() {
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ReadyQueue *QSrc = Pending[IDAlu];
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for (ReadyQueue::iterator I = QSrc->begin(),
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E = QSrc->end(); I != E; ++I) {
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(*I)->NodeQueueId &= ~QSrc->getID();
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AluKind AK = getAluKind(*I);
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AvailableAlus[AK].insert(*I);
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}
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QSrc->clear();
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}
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void R600SchedStrategy::PrepareNextSlot() {
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DEBUG(dbgs() << "New Slot\n");
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assert (OccupedSlotsMask && "Slot wasn't filled");
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OccupedSlotsMask = 0;
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InstructionsGroupCandidate.clear();
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LoadAlu();
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}
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void R600SchedStrategy::AssignSlot(MachineInstr* MI, unsigned Slot) {
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unsigned DestReg = MI->getOperand(0).getReg();
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// PressureRegister crashes if an operand is def and used in the same inst
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// and we try to constraint its regclass
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for (MachineInstr::mop_iterator It = MI->operands_begin(),
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E = MI->operands_end(); It != E; ++It) {
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MachineOperand &MO = *It;
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if (MO.isReg() && !MO.isDef() &&
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MO.getReg() == MI->getOperand(0).getReg())
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return;
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}
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// Constrains the regclass of DestReg to assign it to Slot
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switch (Slot) {
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case 0:
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MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_XRegClass);
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break;
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case 1:
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MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_YRegClass);
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break;
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case 2:
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MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass);
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break;
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case 3:
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MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_WRegClass);
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break;
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}
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}
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SUnit *R600SchedStrategy::AttemptFillSlot(unsigned Slot) {
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static const AluKind IndexToID[] = {AluT_X, AluT_Y, AluT_Z, AluT_W};
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SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]]);
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SUnit *UnslotedSU = PopInst(AvailableAlus[AluAny]);
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if (!UnslotedSU) {
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return SlotedSU;
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} else if (!SlotedSU) {
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AssignSlot(UnslotedSU->getInstr(), Slot);
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return UnslotedSU;
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} else {
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//Determine which one to pick (the lesser one)
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if (CompareSUnit()(SlotedSU, UnslotedSU)) {
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AvailableAlus[AluAny].insert(UnslotedSU);
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return SlotedSU;
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} else {
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AvailableAlus[IndexToID[Slot]].insert(SlotedSU);
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AssignSlot(UnslotedSU->getInstr(), Slot);
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return UnslotedSU;
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}
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}
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}
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bool R600SchedStrategy::isAvailablesAluEmpty() const {
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return Pending[IDAlu]->empty() && AvailableAlus[AluAny].empty() &&
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AvailableAlus[AluT_XYZW].empty() && AvailableAlus[AluT_X].empty() &&
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AvailableAlus[AluT_Y].empty() && AvailableAlus[AluT_Z].empty() &&
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AvailableAlus[AluT_W].empty() && AvailableAlus[AluDiscarded].empty();
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}
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SUnit* R600SchedStrategy::pickAlu() {
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while (!isAvailablesAluEmpty()) {
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if (!OccupedSlotsMask) {
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// Flush physical reg copies (RA will discard them)
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if (!AvailableAlus[AluDiscarded].empty()) {
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OccupedSlotsMask = 15;
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return PopInst(AvailableAlus[AluDiscarded]);
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}
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// If there is a T_XYZW alu available, use it
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if (!AvailableAlus[AluT_XYZW].empty()) {
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OccupedSlotsMask = 15;
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return PopInst(AvailableAlus[AluT_XYZW]);
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}
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}
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for (unsigned Chan = 0; Chan < 4; ++Chan) {
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bool isOccupied = OccupedSlotsMask & (1 << Chan);
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if (!isOccupied) {
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SUnit *SU = AttemptFillSlot(Chan);
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if (SU) {
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OccupedSlotsMask |= (1 << Chan);
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InstructionsGroupCandidate.push_back(SU->getInstr());
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return SU;
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}
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}
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}
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PrepareNextSlot();
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}
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return NULL;
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}
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SUnit* R600SchedStrategy::pickOther(int QID) {
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SUnit *SU = 0;
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ReadyQueue *AQ = Available[QID];
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if (AQ->empty()) {
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MoveUnits(Pending[QID], AQ);
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}
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if (!AQ->empty()) {
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SU = *AQ->begin();
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AQ->remove(AQ->begin());
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}
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return SU;
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}
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