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d0702afadf
------------------------------------------------------------------------ r243638 | vkalintiris | 2015-07-30 05:39:33 -0700 (Thu, 30 Jul 2015) | 12 lines [mips][FastISel] Remove hidden mips-fast-isel option. Summary: This hidden option would disable code generation through FastISel by default. It was removed from the available options and from the Fast-ISel tests that required it in order to run the tests. Reviewers: dsanders Subscribers: qcolombet, llvm-commits Differential Revision: http://reviews.llvm.org/D11610 ------------------------------------------------------------------------ ------------------------------------------------------------------------ r243640 | vkalintiris | 2015-07-30 06:13:09 -0700 (Thu, 30 Jul 2015) | 5 lines [mips] Fix out-of-date debug information in test file. Update the debug info in the check-lines because the change in r243638 introduced a constant initialization before the prologue's end as part of a register spill. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_37@243650 91177308-0d34-0410-b5e6-96231b3b80d8
59 lines
2.1 KiB
LLVM
59 lines
2.1 KiB
LLVM
; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
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; RUN: -fast-isel-abort=1 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=32R1
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; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
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; RUN: -fast-isel-abort=1 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=32R2
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@a = global i16 -21829, align 2
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@b = global i32 -1430532899, align 4
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@a1 = common global i16 0, align 2
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@b1 = common global i32 0, align 4
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declare i16 @llvm.bswap.i16(i16)
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declare i32 @llvm.bswap.i32(i32)
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define void @b16() {
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; ALL-LABEL: b16:
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; ALL: lw $[[A_ADDR:[0-9]+]], %got(a)($[[GOT_ADDR:[0-9]+]])
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; ALL: lhu $[[A_VAL:[0-9]+]], 0($[[A_ADDR]])
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; 32R1: sll $[[TMP1:[0-9]+]], $[[A_VAL]], 8
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; 32R1: srl $[[TMP2:[0-9]+]], $[[A_VAL]], 8
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; 32R1: or $[[TMP3:[0-9]+]], $[[TMP1]], $[[TMP2]]
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; 32R1: andi $[[TMP4:[0-9]+]], $[[TMP3]], 65535
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; 32R2: wsbh $[[RESULT:[0-9]+]], $[[A_VAL]]
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%1 = load i16, i16* @a, align 2
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%2 = call i16 @llvm.bswap.i16(i16 %1)
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store i16 %2, i16* @a1, align 2
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ret void
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}
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define void @b32() {
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; ALL-LABEL: b32:
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; ALL: lw $[[B_ADDR:[0-9]+]], %got(b)($[[GOT_ADDR:[0-9]+]])
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; ALL: lw $[[B_VAL:[0-9]+]], 0($[[B_ADDR]])
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; 32R1: srl $[[TMP1:[0-9]+]], $[[B_VAL]], 8
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; 32R1: srl $[[TMP2:[0-9]+]], $[[B_VAL]], 24
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; 32R1: andi $[[TMP3:[0-9]+]], $[[TMP1]], 65280
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; 32R1: or $[[TMP4:[0-9]+]], $[[TMP2]], $[[TMP3]]
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; 32R1: andi $[[TMP5:[0-9]+]], $[[B_VAL]], 65280
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; 32R1: sll $[[TMP6:[0-9]+]], $[[TMP5]], 8
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; 32R1: sll $[[TMP7:[0-9]+]], $[[B_VAL]], 24
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; 32R1: or $[[TMP8:[0-9]+]], $[[TMP4]], $[[TMP6]]
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; 32R1: or $[[RESULT:[0-9]+]], $[[TMP7]], $[[TMP8]]
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; 32R2: wsbh $[[TMP:[0-9]+]], $[[B_VAL]]
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; 32R2: rotr $[[RESULT:[0-9]+]], $[[TMP]], 16
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%1 = load i32, i32* @b, align 4
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%2 = call i32 @llvm.bswap.i32(i32 %1)
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store i32 %2, i32* @b1, align 4
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ret void
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}
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