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https://github.com/c64scene-ar/llvm-6502.git
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d8149c1bef
parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133736 91177308-0d34-0410-b5e6-96231b3b80d8
18 lines
510 B
LLVM
18 lines
510 B
LLVM
; RUN: llc < %s -march=ptx32 -mattr=+sm13 | FileCheck %s
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define ptx_device float @t1_f32(float %x, float %y, float %z) {
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; CHECK: mad.rn.f32 r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}};
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; CHECK-NEXT: ret;
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%a = fmul float %x, %y
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%b = fadd float %a, %z
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ret float %b
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}
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define ptx_device double @t1_f64(double %x, double %y, double %z) {
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; CHECK: mad.rn.f64 rd{{[0-9]+}}, rd{{[0-9]+}}, rd{{[0-9]+}}, rd{{[0-9]+}};
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; CHECK-NEXT: ret;
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%a = fmul double %x, %y
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%b = fadd double %a, %z
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ret double %b
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}
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