mirror of
https://github.com/c64scene-ar/llvm-6502.git
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78e6e00922
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108567 91177308-0d34-0410-b5e6-96231b3b80d8
523 lines
17 KiB
C++
523 lines
17 KiB
C++
//===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsInstrInfo.h"
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#include "MipsTargetMachine.h"
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#include "MipsMachineFunction.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "MipsGenInstrInfo.inc"
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using namespace llvm;
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MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
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: TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)),
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TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
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static bool isZeroImm(const MachineOperand &op) {
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return op.isImm() && op.getImm() == 0;
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}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned MipsInstrInfo::
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isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
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{
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if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
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(MI->getOpcode() == Mips::LDC1)) {
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if ((MI->getOperand(2).isFI()) && // is a stack slot
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(MI->getOperand(1).isImm()) && // the imm is zero
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(isZeroImm(MI->getOperand(1)))) {
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FrameIndex = MI->getOperand(2).getIndex();
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return MI->getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned MipsInstrInfo::
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isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
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{
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if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
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(MI->getOpcode() == Mips::SDC1)) {
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if ((MI->getOperand(2).isFI()) && // is a stack slot
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(MI->getOperand(1).isImm()) && // the imm is zero
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(isZeroImm(MI->getOperand(1)))) {
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FrameIndex = MI->getOperand(2).getIndex();
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return MI->getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// insertNoop - If data hazard condition is found insert the target nop
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/// instruction.
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void MipsInstrInfo::
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insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
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{
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DebugLoc DL;
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BuildMI(MBB, MI, DL, get(Mips::NOP));
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}
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void MipsInstrInfo::
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copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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bool DestCPU = Mips::CPURegsRegClass.contains(DestReg);
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bool SrcCPU = Mips::CPURegsRegClass.contains(SrcReg);
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// CPU-CPU is the most common.
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if (DestCPU && SrcCPU) {
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BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
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.addReg(SrcReg, getKillRegState(KillSrc));
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return;
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}
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// Copy to CPU from other registers.
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if (DestCPU) {
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if (Mips::CCRRegClass.contains(SrcReg))
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BuildMI(MBB, I, DL, get(Mips::CFC1), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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else if (Mips::FGR32RegClass.contains(SrcReg))
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BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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else if (SrcReg == Mips::HI)
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BuildMI(MBB, I, DL, get(Mips::MFHI), DestReg);
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else if (SrcReg == Mips::LO)
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BuildMI(MBB, I, DL, get(Mips::MFLO), DestReg);
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else
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llvm_unreachable("Copy to CPU from invalid register");
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return;
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}
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// Copy to other registers from CPU.
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if (SrcCPU) {
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if (Mips::CCRRegClass.contains(DestReg))
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BuildMI(MBB, I, DL, get(Mips::CTC1), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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else if (Mips::FGR32RegClass.contains(DestReg))
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BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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else if (DestReg == Mips::HI)
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BuildMI(MBB, I, DL, get(Mips::MTHI))
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.addReg(SrcReg, getKillRegState(KillSrc));
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else if (DestReg == Mips::LO)
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BuildMI(MBB, I, DL, get(Mips::MTLO))
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.addReg(SrcReg, getKillRegState(KillSrc));
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else
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llvm_unreachable("Copy from CPU to invalid register");
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return;
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}
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if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) {
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BuildMI(MBB, I, DL, get(Mips::FMOV_S32), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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return;
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}
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if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) {
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BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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return;
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}
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if (Mips::CCRRegClass.contains(DestReg, SrcReg)) {
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BuildMI(MBB, I, DL, get(Mips::MOVCCRToCCR), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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return;
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}
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llvm_unreachable("Cannot copy registers");
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}
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void MipsInstrInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (RC == Mips::CPURegsRegisterClass)
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BuildMI(MBB, I, DL, get(Mips::SW)).addReg(SrcReg, getKillRegState(isKill))
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.addImm(0).addFrameIndex(FI);
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else if (RC == Mips::FGR32RegisterClass)
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BuildMI(MBB, I, DL, get(Mips::SWC1)).addReg(SrcReg, getKillRegState(isKill))
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.addImm(0).addFrameIndex(FI);
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else if (RC == Mips::AFGR64RegisterClass) {
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if (!TM.getSubtarget<MipsSubtarget>().isMips1()) {
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BuildMI(MBB, I, DL, get(Mips::SDC1))
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.addReg(SrcReg, getKillRegState(isKill))
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.addImm(0).addFrameIndex(FI);
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} else {
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const TargetRegisterInfo *TRI =
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MBB.getParent()->getTarget().getRegisterInfo();
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const unsigned *SubSet = TRI->getSubRegisters(SrcReg);
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BuildMI(MBB, I, DL, get(Mips::SWC1))
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.addReg(SubSet[0], getKillRegState(isKill))
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.addImm(0).addFrameIndex(FI);
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BuildMI(MBB, I, DL, get(Mips::SWC1))
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.addReg(SubSet[1], getKillRegState(isKill))
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.addImm(4).addFrameIndex(FI);
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}
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} else
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llvm_unreachable("Register class not handled!");
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}
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void MipsInstrInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const
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{
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (RC == Mips::CPURegsRegisterClass)
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BuildMI(MBB, I, DL, get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI);
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else if (RC == Mips::FGR32RegisterClass)
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BuildMI(MBB, I, DL, get(Mips::LWC1), DestReg).addImm(0).addFrameIndex(FI);
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else if (RC == Mips::AFGR64RegisterClass) {
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if (!TM.getSubtarget<MipsSubtarget>().isMips1()) {
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BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg).addImm(0).addFrameIndex(FI);
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} else {
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const TargetRegisterInfo *TRI =
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MBB.getParent()->getTarget().getRegisterInfo();
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const unsigned *SubSet = TRI->getSubRegisters(DestReg);
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BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[0])
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.addImm(0).addFrameIndex(FI);
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BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[1])
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.addImm(4).addFrameIndex(FI);
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}
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} else
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llvm_unreachable("Register class not handled!");
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}
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//===----------------------------------------------------------------------===//
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// Branch Analysis
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//===----------------------------------------------------------------------===//
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/// GetCondFromBranchOpc - Return the Mips CC that matches
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/// the correspondent Branch instruction opcode.
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static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc)
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{
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switch (BrOpc) {
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default: return Mips::COND_INVALID;
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case Mips::BEQ : return Mips::COND_E;
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case Mips::BNE : return Mips::COND_NE;
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case Mips::BGTZ : return Mips::COND_GZ;
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case Mips::BGEZ : return Mips::COND_GEZ;
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case Mips::BLTZ : return Mips::COND_LZ;
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case Mips::BLEZ : return Mips::COND_LEZ;
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// We dont do fp branch analysis yet!
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case Mips::BC1T :
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case Mips::BC1F : return Mips::COND_INVALID;
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}
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}
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/// GetCondBranchFromCond - Return the Branch instruction
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/// opcode that matches the cc.
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unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
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{
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switch (CC) {
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default: llvm_unreachable("Illegal condition code!");
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case Mips::COND_E : return Mips::BEQ;
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case Mips::COND_NE : return Mips::BNE;
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case Mips::COND_GZ : return Mips::BGTZ;
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case Mips::COND_GEZ : return Mips::BGEZ;
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case Mips::COND_LZ : return Mips::BLTZ;
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case Mips::COND_LEZ : return Mips::BLEZ;
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case Mips::FCOND_F:
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case Mips::FCOND_UN:
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case Mips::FCOND_EQ:
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case Mips::FCOND_UEQ:
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case Mips::FCOND_OLT:
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case Mips::FCOND_ULT:
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case Mips::FCOND_OLE:
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case Mips::FCOND_ULE:
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case Mips::FCOND_SF:
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case Mips::FCOND_NGLE:
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case Mips::FCOND_SEQ:
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case Mips::FCOND_NGL:
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case Mips::FCOND_LT:
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case Mips::FCOND_NGE:
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case Mips::FCOND_LE:
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case Mips::FCOND_NGT: return Mips::BC1T;
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case Mips::FCOND_T:
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case Mips::FCOND_OR:
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case Mips::FCOND_NEQ:
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case Mips::FCOND_OGL:
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case Mips::FCOND_UGE:
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case Mips::FCOND_OGE:
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case Mips::FCOND_UGT:
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case Mips::FCOND_OGT:
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case Mips::FCOND_ST:
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case Mips::FCOND_GLE:
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case Mips::FCOND_SNE:
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case Mips::FCOND_GL:
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case Mips::FCOND_NLT:
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case Mips::FCOND_GE:
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case Mips::FCOND_NLE:
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case Mips::FCOND_GT: return Mips::BC1F;
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}
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}
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/// GetOppositeBranchCondition - Return the inverse of the specified
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/// condition, e.g. turning COND_E to COND_NE.
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Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
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{
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switch (CC) {
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default: llvm_unreachable("Illegal condition code!");
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case Mips::COND_E : return Mips::COND_NE;
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case Mips::COND_NE : return Mips::COND_E;
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case Mips::COND_GZ : return Mips::COND_LEZ;
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case Mips::COND_GEZ : return Mips::COND_LZ;
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case Mips::COND_LZ : return Mips::COND_GEZ;
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case Mips::COND_LEZ : return Mips::COND_GZ;
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case Mips::FCOND_F : return Mips::FCOND_T;
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case Mips::FCOND_UN : return Mips::FCOND_OR;
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case Mips::FCOND_EQ : return Mips::FCOND_NEQ;
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case Mips::FCOND_UEQ: return Mips::FCOND_OGL;
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case Mips::FCOND_OLT: return Mips::FCOND_UGE;
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case Mips::FCOND_ULT: return Mips::FCOND_OGE;
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case Mips::FCOND_OLE: return Mips::FCOND_UGT;
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case Mips::FCOND_ULE: return Mips::FCOND_OGT;
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case Mips::FCOND_SF: return Mips::FCOND_ST;
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case Mips::FCOND_NGLE:return Mips::FCOND_GLE;
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case Mips::FCOND_SEQ: return Mips::FCOND_SNE;
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case Mips::FCOND_NGL: return Mips::FCOND_GL;
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case Mips::FCOND_LT: return Mips::FCOND_NLT;
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case Mips::FCOND_NGE: return Mips::FCOND_GE;
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case Mips::FCOND_LE: return Mips::FCOND_NLE;
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case Mips::FCOND_NGT: return Mips::FCOND_GT;
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}
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}
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bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const
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{
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin())
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return false;
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--I;
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while (I->isDebugValue()) {
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if (I == MBB.begin())
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return false;
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--I;
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}
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if (!isUnpredicatedTerminator(I))
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return false;
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// Get the last instruction in the block.
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MachineInstr *LastInst = I;
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// If there is only one terminator instruction, process it.
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unsigned LastOpc = LastInst->getOpcode();
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if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
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if (!LastInst->getDesc().isBranch())
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return true;
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// Unconditional branch
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if (LastOpc == Mips::J) {
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TBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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Mips::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
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if (BranchCode == Mips::COND_INVALID)
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return true; // Can't handle indirect branch.
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// Conditional branch
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// Block ends with fall-through condbranch.
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if (LastOpc != Mips::COND_INVALID) {
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int LastNumOp = LastInst->getNumOperands();
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TBB = LastInst->getOperand(LastNumOp-1).getMBB();
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Cond.push_back(MachineOperand::CreateImm(BranchCode));
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for (int i=0; i<LastNumOp-1; i++) {
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Cond.push_back(LastInst->getOperand(i));
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}
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return false;
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}
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}
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// Get the instruction before it if it is a terminator.
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MachineInstr *SecondLastInst = I;
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// If there are three terminators, we don't know what sort of block this is.
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if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
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return true;
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// If the block ends with Mips::J and a Mips::BNE/Mips::BEQ, handle it.
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unsigned SecondLastOpc = SecondLastInst->getOpcode();
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Mips::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
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if (BranchCode != Mips::COND_INVALID && LastOpc == Mips::J) {
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int SecondNumOp = SecondLastInst->getNumOperands();
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TBB = SecondLastInst->getOperand(SecondNumOp-1).getMBB();
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Cond.push_back(MachineOperand::CreateImm(BranchCode));
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for (int i=0; i<SecondNumOp-1; i++) {
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Cond.push_back(SecondLastInst->getOperand(i));
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}
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FBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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// If the block ends with two unconditional branches, handle it. The last
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// one is not executed, so remove it.
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if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) {
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TBB = SecondLastInst->getOperand(0).getMBB();
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I = LastInst;
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if (AllowModify)
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I->eraseFromParent();
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return false;
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}
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// Otherwise, can't handle this.
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return true;
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}
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unsigned MipsInstrInfo::
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InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const {
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
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"Mips branch conditions can have two|three components!");
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if (FBB == 0) { // One way branch.
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if (Cond.empty()) {
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// Unconditional branch?
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BuildMI(&MBB, DL, get(Mips::J)).addMBB(TBB);
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} else {
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// Conditional branch.
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unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
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const TargetInstrDesc &TID = get(Opc);
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if (TID.getNumOperands() == 3)
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BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg())
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.addReg(Cond[2].getReg())
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.addMBB(TBB);
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else
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BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg())
|
|
.addMBB(TBB);
|
|
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
// Two-way Conditional branch.
|
|
unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
|
|
const TargetInstrDesc &TID = get(Opc);
|
|
|
|
if (TID.getNumOperands() == 3)
|
|
BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
|
|
.addMBB(TBB);
|
|
else
|
|
BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg()).addMBB(TBB);
|
|
|
|
BuildMI(&MBB, DL, get(Mips::J)).addMBB(FBB);
|
|
return 2;
|
|
}
|
|
|
|
unsigned MipsInstrInfo::
|
|
RemoveBranch(MachineBasicBlock &MBB) const
|
|
{
|
|
MachineBasicBlock::iterator I = MBB.end();
|
|
if (I == MBB.begin()) return 0;
|
|
--I;
|
|
while (I->isDebugValue()) {
|
|
if (I == MBB.begin())
|
|
return 0;
|
|
--I;
|
|
}
|
|
if (I->getOpcode() != Mips::J &&
|
|
GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
|
|
return 0;
|
|
|
|
// Remove the branch.
|
|
I->eraseFromParent();
|
|
|
|
I = MBB.end();
|
|
|
|
if (I == MBB.begin()) return 1;
|
|
--I;
|
|
if (GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
|
|
return 1;
|
|
|
|
// Remove the branch.
|
|
I->eraseFromParent();
|
|
return 2;
|
|
}
|
|
|
|
/// ReverseBranchCondition - Return the inverse opcode of the
|
|
/// specified Branch instruction.
|
|
bool MipsInstrInfo::
|
|
ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
|
|
{
|
|
assert( (Cond.size() == 3 || Cond.size() == 2) &&
|
|
"Invalid Mips branch condition!");
|
|
Cond[0].setImm(GetOppositeBranchCondition((Mips::CondCode)Cond[0].getImm()));
|
|
return false;
|
|
}
|
|
|
|
/// getGlobalBaseReg - Return a virtual register initialized with the
|
|
/// the global base register value. Output instructions required to
|
|
/// initialize the register in the function entry block, if necessary.
|
|
///
|
|
unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
|
|
MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
|
|
unsigned GlobalBaseReg = MipsFI->getGlobalBaseReg();
|
|
if (GlobalBaseReg != 0)
|
|
return GlobalBaseReg;
|
|
|
|
// Insert the set of GlobalBaseReg into the first MBB of the function
|
|
MachineBasicBlock &FirstMBB = MF->front();
|
|
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
|
|
MachineRegisterInfo &RegInfo = MF->getRegInfo();
|
|
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
|
|
|
|
GlobalBaseReg = RegInfo.createVirtualRegister(Mips::CPURegsRegisterClass);
|
|
BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
|
|
GlobalBaseReg).addReg(Mips::GP);
|
|
RegInfo.addLiveIn(Mips::GP);
|
|
|
|
MipsFI->setGlobalBaseReg(GlobalBaseReg);
|
|
return GlobalBaseReg;
|
|
}
|