mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-13 10:32:06 +00:00
d30a98e43a
(RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98637 91177308-0d34-0410-b5e6-96231b3b80d8
25 lines
864 B
Makefile
25 lines
864 B
Makefile
##===- lib/Target/ARM/Makefile -----------------------------*- Makefile -*-===##
|
|
#
|
|
# The LLVM Compiler Infrastructure
|
|
#
|
|
# This file is distributed under the University of Illinois Open Source
|
|
# License. See LICENSE.TXT for details.
|
|
#
|
|
##===----------------------------------------------------------------------===##
|
|
|
|
LEVEL = ../../..
|
|
LIBRARYNAME = LLVMARMCodeGen
|
|
TARGET = ARM
|
|
|
|
# Make sure that tblgen is run, first thing.
|
|
BUILT_SOURCES = ARMGenRegisterInfo.h.inc ARMGenRegisterNames.inc \
|
|
ARMGenRegisterInfo.inc ARMGenInstrNames.inc \
|
|
ARMGenInstrInfo.inc ARMGenAsmWriter.inc \
|
|
ARMGenDAGISel.inc ARMGenSubtarget.inc \
|
|
ARMGenCodeEmitter.inc ARMGenCallingConv.inc \
|
|
ARMGenDisassemblerTables.inc
|
|
|
|
DIRS = AsmPrinter AsmParser Disassembler TargetInfo
|
|
|
|
include $(LEVEL)/Makefile.common
|