Bill Wendling d36d03bf2d Added a check so that if we have two machine instructions in this form ... MOV R0, R1 MOV R1, R0 the second machine instruction is removed. Added a regression test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29792 91177308-0d34-0410-b5e6-96231b3b80d8		2006-08-21 07:33:33 +00:00
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Analysis
Archive
AsmParser	regenerate	2006-08-18 17:34:45 +00:00
Bytecode
CodeGen	Added a check so that if we have two machine instructions in this form	2006-08-21 07:33:33 +00:00
Debugger
ExecutionEngine	initial changes to support JIT'ing from multiple module providers, implicitly	2006-08-16 01:24:12 +00:00
Linker
Support	For PR797:	2006-08-21 06:04:45 +00:00
System	For PR797:	2006-08-21 06:02:44 +00:00
Target	call computeRegisterProperties	2006-08-20 01:49:49 +00:00
Transforms	Fix a grammaro in a comment.	2006-08-18 09:01:07 +00:00
VMCore
Makefile