Alexey Samsonov 84e51517e2 Tentative fix for global-buffer-overflow caused by r188426. Found by AddressSanitizer ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188448 91177308-0d34-0410-b5e6-96231b3b80d8

2013-08-15 07:11:34 +00:00

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InstPrinter

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MCTargetDesc

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TargetInfo

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AMDGPU.h

R600/SI: Convert v16i8 resource descriptors to i128

2013-08-14 23:24:45 +00:00

AMDGPU.td

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AMDGPUAsmPrinter.cpp

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AMDGPUAsmPrinter.h

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AMDGPUCallingConv.td

R600/SI: Fix an obvious typo

2013-08-14 22:22:03 +00:00

AMDGPUConvertToISA.cpp

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AMDGPUFrameLowering.cpp

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AMDGPUFrameLowering.h

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AMDGPUIndirectAddressing.cpp

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AMDGPUInstrInfo.cpp

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AMDGPUInstrInfo.h

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AMDGPUInstrInfo.td

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AMDGPUInstructions.td

R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2

2013-08-14 23:24:32 +00:00

AMDGPUIntrinsics.td

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AMDGPUISelDAGToDAG.cpp

Tentative fix for global-buffer-overflow caused by r188426. Found by AddressSanitizer

2013-08-15 07:11:34 +00:00

AMDGPUISelLowering.cpp

R600/SI: Improve legalization of vector operations

2013-08-14 23:25:00 +00:00

AMDGPUISelLowering.h

R600/SI: Improve legalization of vector operations

2013-08-14 23:25:00 +00:00

AMDGPUMachineFunction.cpp

Move string pointer from being a static class member to just a static global in the one file its needed in.

2013-07-17 00:31:35 +00:00

AMDGPUMachineFunction.h

Move string pointer from being a static class member to just a static global in the one file its needed in.

2013-07-17 00:31:35 +00:00

AMDGPUMCInstLower.cpp

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AMDGPUMCInstLower.h

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AMDGPURegisterInfo.cpp

R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2

2013-08-14 23:24:32 +00:00

AMDGPURegisterInfo.h

R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2

2013-08-14 23:24:32 +00:00

AMDGPURegisterInfo.td

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AMDGPUSubtarget.cpp

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AMDGPUSubtarget.h

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AMDGPUTargetMachine.cpp

R600/SI: Convert v16i8 resource descriptors to i128

2013-08-14 23:24:45 +00:00

AMDGPUTargetMachine.h

SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions

2013-07-27 00:01:07 +00:00

AMDGPUTargetTransformInfo.cpp

SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions

2013-07-27 00:01:07 +00:00

AMDILBase.td

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AMDILCFGStructurizer.cpp

R600: Remove predicated_break inst

2013-07-31 19:31:14 +00:00

AMDILInstrInfo.td

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AMDILIntrinsicInfo.cpp

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AMDILIntrinsicInfo.h

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AMDILIntrinsics.td

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AMDILISelLowering.cpp

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AMDILRegisterInfo.td

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CMakeLists.txt

R600/SI: Convert v16i8 resource descriptors to i128

2013-08-14 23:24:45 +00:00

LLVMBuild.txt

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Makefile

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Processors.td

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R600ControlFlowFinalizer.cpp

R600: Add 64-bit float load/store support

2013-08-01 15:23:42 +00:00

R600Defines.h

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R600EmitClauseMarkers.cpp

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R600ExpandSpecialInstrs.cpp

R600: Remove predicated_break inst

2013-07-31 19:31:14 +00:00

R600InstrFormats.td

Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"

2013-07-31 20:43:03 +00:00

R600InstrInfo.cpp

R600: Add 64-bit float load/store support

2013-08-01 15:23:42 +00:00

R600InstrInfo.h

Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"

2013-07-31 20:43:03 +00:00

R600Instructions.td

R600/SI: Handle MSAA texture targets

2013-08-14 22:22:14 +00:00

R600Intrinsics.td

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R600ISelLowering.cpp

R600: Set scheduling preference to Sched::Source

2013-08-12 22:33:21 +00:00

R600ISelLowering.h

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R600MachineFunctionInfo.cpp

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R600MachineFunctionInfo.h

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R600MachineScheduler.cpp

Revert "R600: Non vector only instruction can be scheduled on trans unit"

2013-07-31 20:43:27 +00:00

R600MachineScheduler.h

Revert "R600: Non vector only instruction can be scheduled on trans unit"

2013-07-31 20:43:27 +00:00

R600OptimizeVectorRegisters.cpp

R600: Do not mergevector after a vector reg is used

2013-07-31 19:32:12 +00:00

R600Packetizer.cpp

Revert "R600: Non vector only instruction can be scheduled on trans unit"

2013-07-31 20:43:27 +00:00

R600RegisterInfo.cpp

R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2

2013-08-14 23:24:32 +00:00

R600RegisterInfo.h

R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2

2013-08-14 23:24:32 +00:00

R600RegisterInfo.td

R600: Add 64-bit float load/store support

2013-08-01 15:23:42 +00:00

R600Schedule.td

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R600TextureIntrinsicsReplacer.cpp

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SIAnnotateControlFlow.cpp

Add 'const' qualifiers to static const char* variables.

2013-07-16 01:17:10 +00:00

SIDefines.h

R600/SI: Assign a register class to the $vaddr operand for MIMG instructions

2013-08-14 23:24:17 +00:00

SIFixSGPRCopies.cpp

R600/SI: Use VSrc_* register classes as the default classes for types

2013-08-06 23:08:28 +00:00

SIInsertWaits.cpp

Initialize SIInsertWaits::ExpInstrTypesSeen in the pass constructor.

2013-08-07 07:47:41 +00:00

SIInstrFormats.td

R600/SI: Assign a register class to the $vaddr operand for MIMG instructions

2013-08-14 23:24:17 +00:00

SIInstrInfo.cpp

R600/SI: Assign a register class to the $vaddr operand for MIMG instructions

2013-08-14 23:24:17 +00:00

SIInstrInfo.h

R600/SI: Assign a register class to the $vaddr operand for MIMG instructions

2013-08-14 23:24:17 +00:00

SIInstrInfo.td

R600/SI: Replace v1i32 type with i32 in imageload and sample intrinsics

2013-08-14 23:24:53 +00:00

SIInstructions.td

R600/SI: Replace v1i32 type with i32 in imageload and sample intrinsics

2013-08-14 23:24:53 +00:00

SIIntrinsics.td

R600/SI: Convert v16i8 resource descriptors to i128

2013-08-14 23:24:45 +00:00

SIISelLowering.cpp

R600/SI: Improve legalization of vector operations

2013-08-14 23:25:00 +00:00

SIISelLowering.h

R600/SI: Improve legalization of vector operations

2013-08-14 23:25:00 +00:00

SILowerControlFlow.cpp

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SIMachineFunctionInfo.cpp

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SIMachineFunctionInfo.h

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SIRegisterInfo.cpp

R600/SI: Choose the correct MOV instruction for copying immediates

2013-08-14 23:24:24 +00:00

SIRegisterInfo.h

R600/SI: Choose the correct MOV instruction for copying immediates

2013-08-14 23:24:24 +00:00

SIRegisterInfo.td

R600/SI: Convert v16i8 resource descriptors to i128

2013-08-14 23:24:45 +00:00

SISchedule.td

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SITypeRewriter.cpp

R600/SI: Replace v1i32 type with i32 in imageload and sample intrinsics

2013-08-14 23:24:53 +00:00