mirror of
https://github.com/c64scene-ar/llvm-6502.git
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8e8b8a223c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57622 91177308-0d34-0410-b5e6-96231b3b80d8
792 lines
29 KiB
C++
792 lines
29 KiB
C++
//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "PPCInstrInfo.h"
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#include "PPCInstrBuilder.h"
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#include "PPCMachineFunctionInfo.h"
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#include "PPCPredicates.h"
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#include "PPCGenInstrInfo.inc"
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#include "PPCTargetMachine.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetAsmInfo.h"
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using namespace llvm;
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extern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
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extern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
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PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
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: TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
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RI(*TM.getSubtargetImpl(), *this) {}
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const {
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if (TM.getSubtargetImpl()->isPPC64())
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return &PPC::G8RCRegClass;
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else
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return &PPC::GPRCRegClass;
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}
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bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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unsigned& destReg) const {
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unsigned oc = MI.getOpcode();
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if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
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oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2
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assert(MI.getNumOperands() >= 3 &&
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MI.getOperand(0).isReg() &&
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MI.getOperand(1).isReg() &&
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MI.getOperand(2).isReg() &&
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"invalid PPC OR instruction!");
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if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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} else if (oc == PPC::ADDI) { // addi r1, r2, 0
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assert(MI.getNumOperands() >= 3 &&
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MI.getOperand(0).isReg() &&
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MI.getOperand(2).isImm() &&
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"invalid PPC ADDI instruction!");
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if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) {
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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} else if (oc == PPC::ORI) { // ori r1, r2, 0
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assert(MI.getNumOperands() >= 3 &&
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MI.getOperand(0).isReg() &&
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MI.getOperand(1).isReg() &&
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MI.getOperand(2).isImm() &&
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"invalid PPC ORI instruction!");
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if (MI.getOperand(2).getImm() == 0) {
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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} else if (oc == PPC::FMRS || oc == PPC::FMRD ||
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oc == PPC::FMRSD) { // fmr r1, r2
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assert(MI.getNumOperands() >= 2 &&
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MI.getOperand(0).isReg() &&
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MI.getOperand(1).isReg() &&
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"invalid PPC FMR instruction");
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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} else if (oc == PPC::MCRF) { // mcrf cr1, cr2
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assert(MI.getNumOperands() >= 2 &&
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MI.getOperand(0).isReg() &&
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MI.getOperand(1).isReg() &&
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"invalid PPC MCRF instruction");
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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return false;
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}
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unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
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int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case PPC::LD:
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case PPC::LWZ:
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case PPC::LFS:
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case PPC::LFD:
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if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
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MI->getOperand(2).isFI()) {
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FrameIndex = MI->getOperand(2).getIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI,
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int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case PPC::STD:
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case PPC::STW:
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case PPC::STFS:
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case PPC::STFD:
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if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
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MI->getOperand(2).isFI()) {
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FrameIndex = MI->getOperand(2).getIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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// commuteInstruction - We can commute rlwimi instructions, but only if the
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// rotate amt is zero. We also have to munge the immediates a bit.
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MachineInstr *
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PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
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MachineFunction &MF = *MI->getParent()->getParent();
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// Normal instructions can be commuted the obvious way.
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if (MI->getOpcode() != PPC::RLWIMI)
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return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
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// Cannot commute if it has a non-zero rotate count.
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if (MI->getOperand(3).getImm() != 0)
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return 0;
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// If we have a zero rotate count, we have:
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// M = mask(MB,ME)
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// Op0 = (Op1 & ~M) | (Op2 & M)
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// Change this to:
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// M = mask((ME+1)&31, (MB-1)&31)
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// Op0 = (Op2 & ~M) | (Op1 & M)
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// Swap op1/op2
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unsigned Reg0 = MI->getOperand(0).getReg();
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unsigned Reg1 = MI->getOperand(1).getReg();
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unsigned Reg2 = MI->getOperand(2).getReg();
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bool Reg1IsKill = MI->getOperand(1).isKill();
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bool Reg2IsKill = MI->getOperand(2).isKill();
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bool ChangeReg0 = false;
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// If machine instrs are no longer in two-address forms, update
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// destination register as well.
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if (Reg0 == Reg1) {
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// Must be two address instruction!
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assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
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"Expecting a two-address instruction!");
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Reg2IsKill = false;
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ChangeReg0 = true;
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}
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// Masks.
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unsigned MB = MI->getOperand(4).getImm();
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unsigned ME = MI->getOperand(5).getImm();
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if (NewMI) {
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// Create a new instruction.
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unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
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bool Reg0IsDead = MI->getOperand(0).isDead();
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return BuildMI(MF, MI->getDesc())
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.addReg(Reg0, true, false, false, Reg0IsDead)
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.addReg(Reg2, false, false, Reg2IsKill)
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.addReg(Reg1, false, false, Reg1IsKill)
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.addImm((ME+1) & 31)
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.addImm((MB-1) & 31);
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}
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if (ChangeReg0)
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MI->getOperand(0).setReg(Reg2);
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MI->getOperand(2).setReg(Reg1);
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MI->getOperand(1).setReg(Reg2);
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MI->getOperand(2).setIsKill(Reg1IsKill);
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MI->getOperand(1).setIsKill(Reg2IsKill);
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// Swap the mask around.
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MI->getOperand(4).setImm((ME+1) & 31);
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MI->getOperand(5).setImm((MB-1) & 31);
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return MI;
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}
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void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const {
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BuildMI(MBB, MI, get(PPC::NOP));
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}
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// Branch analysis.
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bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond) const {
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
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return false;
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// Get the last instruction in the block.
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MachineInstr *LastInst = I;
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// If there is only one terminator instruction, process it.
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if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
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if (LastInst->getOpcode() == PPC::B) {
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TBB = LastInst->getOperand(0).getMBB();
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return false;
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} else if (LastInst->getOpcode() == PPC::BCC) {
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// Block ends with fall-through condbranch.
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TBB = LastInst->getOperand(2).getMBB();
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Cond.push_back(LastInst->getOperand(0));
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Cond.push_back(LastInst->getOperand(1));
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return false;
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}
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// Otherwise, don't know what this is.
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return true;
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}
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// Get the instruction before it if it's a terminator.
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MachineInstr *SecondLastInst = I;
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// If there are three terminators, we don't know what sort of block this is.
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if (SecondLastInst && I != MBB.begin() &&
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isUnpredicatedTerminator(--I))
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return true;
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// If the block ends with PPC::B and PPC:BCC, handle it.
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if (SecondLastInst->getOpcode() == PPC::BCC &&
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LastInst->getOpcode() == PPC::B) {
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TBB = SecondLastInst->getOperand(2).getMBB();
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Cond.push_back(SecondLastInst->getOperand(0));
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Cond.push_back(SecondLastInst->getOperand(1));
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FBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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// If the block ends with two PPC:Bs, handle it. The second one is not
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// executed, so remove it.
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if (SecondLastInst->getOpcode() == PPC::B &&
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LastInst->getOpcode() == PPC::B) {
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TBB = SecondLastInst->getOperand(0).getMBB();
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I = LastInst;
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I->eraseFromParent();
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return false;
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}
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// Otherwise, can't handle this.
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return true;
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}
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unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin()) return 0;
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--I;
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if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
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return 0;
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// Remove the branch.
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I->eraseFromParent();
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I = MBB.end();
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if (I == MBB.begin()) return 1;
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--I;
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if (I->getOpcode() != PPC::BCC)
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return 1;
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// Remove the branch.
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I->eraseFromParent();
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return 2;
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}
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unsigned
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PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const {
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 2 || Cond.size() == 0) &&
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"PPC branch conditions have two components!");
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// One-way branch.
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if (FBB == 0) {
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if (Cond.empty()) // Unconditional branch
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BuildMI(&MBB, get(PPC::B)).addMBB(TBB);
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else // Conditional branch
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BuildMI(&MBB, get(PPC::BCC))
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.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
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return 1;
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}
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// Two-way Conditional Branch.
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BuildMI(&MBB, get(PPC::BCC))
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.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
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BuildMI(&MBB, get(PPC::B)).addMBB(FBB);
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return 2;
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}
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bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const {
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if (DestRC != SrcRC) {
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// Not yet supported!
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return false;
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}
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if (DestRC == PPC::GPRCRegisterClass) {
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BuildMI(MBB, MI, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
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} else if (DestRC == PPC::G8RCRegisterClass) {
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BuildMI(MBB, MI, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
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} else if (DestRC == PPC::F4RCRegisterClass) {
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BuildMI(MBB, MI, get(PPC::FMRS), DestReg).addReg(SrcReg);
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} else if (DestRC == PPC::F8RCRegisterClass) {
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BuildMI(MBB, MI, get(PPC::FMRD), DestReg).addReg(SrcReg);
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} else if (DestRC == PPC::CRRCRegisterClass) {
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BuildMI(MBB, MI, get(PPC::MCRF), DestReg).addReg(SrcReg);
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} else if (DestRC == PPC::VRRCRegisterClass) {
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BuildMI(MBB, MI, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
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} else if (DestRC == PPC::CRBITRCRegisterClass) {
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BuildMI(MBB, MI, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
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} else {
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// Attempt to copy register that is not GPR or FPR
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return false;
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}
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return true;
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}
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bool
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PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
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unsigned SrcReg, bool isKill,
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int FrameIdx,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const{
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if (RC == PPC::GPRCRegisterClass) {
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if (SrcReg != PPC::LR) {
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NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
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.addReg(SrcReg, false, false, isKill),
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FrameIdx));
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} else {
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// FIXME: this spills LR immediately to memory in one step. To do this,
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// we use R11, which we know cannot be used in the prolog/epilog. This is
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// a hack.
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NewMIs.push_back(BuildMI(MF, get(PPC::MFLR), PPC::R11));
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NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
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.addReg(PPC::R11, false, false, isKill),
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FrameIdx));
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}
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} else if (RC == PPC::G8RCRegisterClass) {
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if (SrcReg != PPC::LR8) {
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NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD))
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.addReg(SrcReg, false, false, isKill), FrameIdx));
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} else {
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// FIXME: this spills LR immediately to memory in one step. To do this,
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// we use R11, which we know cannot be used in the prolog/epilog. This is
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// a hack.
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NewMIs.push_back(BuildMI(MF, get(PPC::MFLR8), PPC::X11));
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NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD))
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.addReg(PPC::X11, false, false, isKill), FrameIdx));
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}
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} else if (RC == PPC::F8RCRegisterClass) {
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NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFD))
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.addReg(SrcReg, false, false, isKill), FrameIdx));
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} else if (RC == PPC::F4RCRegisterClass) {
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NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFS))
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.addReg(SrcReg, false, false, isKill), FrameIdx));
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} else if (RC == PPC::CRRCRegisterClass) {
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if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
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(EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
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// FIXME (64-bit): Enable
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NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::SPILL_CR))
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.addReg(SrcReg, false, false, isKill),
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FrameIdx));
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return true;
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} else {
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// FIXME: We use R0 here, because it isn't available for RA. We need to
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// store the CR in the low 4-bits of the saved value. First, issue a MFCR
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// to save all of the CRBits.
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NewMIs.push_back(BuildMI(MF, get(PPC::MFCR), PPC::R0));
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// If the saved register wasn't CR0, shift the bits left so that they are
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// in CR0's slot.
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if (SrcReg != PPC::CR0) {
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unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
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// rlwinm r0, r0, ShiftBits, 0, 31.
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NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0)
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.addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
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}
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NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
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.addReg(PPC::R0, false, false, isKill),
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FrameIdx));
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}
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} else if (RC == PPC::CRBITRCRegisterClass) {
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// FIXME: We use CRi here because there is no mtcrf on a bit. Since the
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// backend currently only uses CR1EQ as an individual bit, this should
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// not cause any bug. If we need other uses of CR bits, the following
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// code may be invalid.
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unsigned Reg = 0;
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if (SrcReg >= PPC::CR0LT || SrcReg <= PPC::CR0UN)
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Reg = PPC::CR0;
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else if (SrcReg >= PPC::CR1LT || SrcReg <= PPC::CR1UN)
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Reg = PPC::CR1;
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else if (SrcReg >= PPC::CR2LT || SrcReg <= PPC::CR2UN)
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Reg = PPC::CR2;
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else if (SrcReg >= PPC::CR3LT || SrcReg <= PPC::CR3UN)
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Reg = PPC::CR3;
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else if (SrcReg >= PPC::CR4LT || SrcReg <= PPC::CR4UN)
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Reg = PPC::CR4;
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else if (SrcReg >= PPC::CR5LT || SrcReg <= PPC::CR5UN)
|
|
Reg = PPC::CR5;
|
|
else if (SrcReg >= PPC::CR6LT || SrcReg <= PPC::CR6UN)
|
|
Reg = PPC::CR6;
|
|
else if (SrcReg >= PPC::CR7LT || SrcReg <= PPC::CR7UN)
|
|
Reg = PPC::CR7;
|
|
|
|
return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
|
|
PPC::CRRCRegisterClass, NewMIs);
|
|
|
|
} else if (RC == PPC::VRRCRegisterClass) {
|
|
// We don't have indexed addressing for vector loads. Emit:
|
|
// R0 = ADDI FI#
|
|
// STVX VAL, 0, R0
|
|
//
|
|
// FIXME: We use R0 here, because it isn't available for RA.
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0),
|
|
FrameIdx, 0, 0));
|
|
NewMIs.push_back(BuildMI(MF, get(PPC::STVX))
|
|
.addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0));
|
|
} else {
|
|
assert(0 && "Unknown regclass!");
|
|
abort();
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
void
|
|
PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
unsigned SrcReg, bool isKill, int FrameIdx,
|
|
const TargetRegisterClass *RC) const {
|
|
MachineFunction &MF = *MBB.getParent();
|
|
SmallVector<MachineInstr*, 4> NewMIs;
|
|
|
|
if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
|
|
PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
|
|
FuncInfo->setSpillsCR();
|
|
}
|
|
|
|
for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
|
|
MBB.insert(MI, NewMIs[i]);
|
|
}
|
|
|
|
void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
|
bool isKill,
|
|
SmallVectorImpl<MachineOperand> &Addr,
|
|
const TargetRegisterClass *RC,
|
|
SmallVectorImpl<MachineInstr*> &NewMIs) const{
|
|
if (Addr[0].isFI()) {
|
|
if (StoreRegToStackSlot(MF, SrcReg, isKill,
|
|
Addr[0].getIndex(), RC, NewMIs)) {
|
|
PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
|
|
FuncInfo->setSpillsCR();
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
unsigned Opc = 0;
|
|
if (RC == PPC::GPRCRegisterClass) {
|
|
Opc = PPC::STW;
|
|
} else if (RC == PPC::G8RCRegisterClass) {
|
|
Opc = PPC::STD;
|
|
} else if (RC == PPC::F8RCRegisterClass) {
|
|
Opc = PPC::STFD;
|
|
} else if (RC == PPC::F4RCRegisterClass) {
|
|
Opc = PPC::STFS;
|
|
} else if (RC == PPC::VRRCRegisterClass) {
|
|
Opc = PPC::STVX;
|
|
} else {
|
|
assert(0 && "Unknown regclass!");
|
|
abort();
|
|
}
|
|
MachineInstrBuilder MIB = BuildMI(MF, get(Opc))
|
|
.addReg(SrcReg, false, false, isKill);
|
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
|
|
MachineOperand &MO = Addr[i];
|
|
if (MO.isReg())
|
|
MIB.addReg(MO.getReg());
|
|
else if (MO.isImm())
|
|
MIB.addImm(MO.getImm());
|
|
else
|
|
MIB.addFrameIndex(MO.getIndex());
|
|
}
|
|
NewMIs.push_back(MIB);
|
|
return;
|
|
}
|
|
|
|
void
|
|
PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF,
|
|
unsigned DestReg, int FrameIdx,
|
|
const TargetRegisterClass *RC,
|
|
SmallVectorImpl<MachineInstr*> &NewMIs)const{
|
|
if (RC == PPC::GPRCRegisterClass) {
|
|
if (DestReg != PPC::LR) {
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), DestReg),
|
|
FrameIdx));
|
|
} else {
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), PPC::R11),
|
|
FrameIdx));
|
|
NewMIs.push_back(BuildMI(MF, get(PPC::MTLR)).addReg(PPC::R11));
|
|
}
|
|
} else if (RC == PPC::G8RCRegisterClass) {
|
|
if (DestReg != PPC::LR8) {
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LD), DestReg),
|
|
FrameIdx));
|
|
} else {
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LD), PPC::R11),
|
|
FrameIdx));
|
|
NewMIs.push_back(BuildMI(MF, get(PPC::MTLR8)).addReg(PPC::R11));
|
|
}
|
|
} else if (RC == PPC::F8RCRegisterClass) {
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LFD), DestReg),
|
|
FrameIdx));
|
|
} else if (RC == PPC::F4RCRegisterClass) {
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LFS), DestReg),
|
|
FrameIdx));
|
|
} else if (RC == PPC::CRRCRegisterClass) {
|
|
// FIXME: We use R0 here, because it isn't available for RA.
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), PPC::R0),
|
|
FrameIdx));
|
|
|
|
// If the reloaded register isn't CR0, shift the bits right so that they are
|
|
// in the right CR's slot.
|
|
if (DestReg != PPC::CR0) {
|
|
unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
|
|
// rlwinm r11, r11, 32-ShiftBits, 0, 31.
|
|
NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0)
|
|
.addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
|
|
}
|
|
|
|
NewMIs.push_back(BuildMI(MF, get(PPC::MTCRF), DestReg).addReg(PPC::R0));
|
|
} else if (RC == PPC::CRBITRCRegisterClass) {
|
|
|
|
unsigned Reg = 0;
|
|
if (DestReg >= PPC::CR0LT || DestReg <= PPC::CR0UN)
|
|
Reg = PPC::CR0;
|
|
else if (DestReg >= PPC::CR1LT || DestReg <= PPC::CR1UN)
|
|
Reg = PPC::CR1;
|
|
else if (DestReg >= PPC::CR2LT || DestReg <= PPC::CR2UN)
|
|
Reg = PPC::CR2;
|
|
else if (DestReg >= PPC::CR3LT || DestReg <= PPC::CR3UN)
|
|
Reg = PPC::CR3;
|
|
else if (DestReg >= PPC::CR4LT || DestReg <= PPC::CR4UN)
|
|
Reg = PPC::CR4;
|
|
else if (DestReg >= PPC::CR5LT || DestReg <= PPC::CR5UN)
|
|
Reg = PPC::CR5;
|
|
else if (DestReg >= PPC::CR6LT || DestReg <= PPC::CR6UN)
|
|
Reg = PPC::CR6;
|
|
else if (DestReg >= PPC::CR7LT || DestReg <= PPC::CR7UN)
|
|
Reg = PPC::CR7;
|
|
|
|
return LoadRegFromStackSlot(MF, Reg, FrameIdx,
|
|
PPC::CRRCRegisterClass, NewMIs);
|
|
|
|
} else if (RC == PPC::VRRCRegisterClass) {
|
|
// We don't have indexed addressing for vector loads. Emit:
|
|
// R0 = ADDI FI#
|
|
// Dest = LVX 0, R0
|
|
//
|
|
// FIXME: We use R0 here, because it isn't available for RA.
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0),
|
|
FrameIdx, 0, 0));
|
|
NewMIs.push_back(BuildMI(MF, get(PPC::LVX),DestReg).addReg(PPC::R0)
|
|
.addReg(PPC::R0));
|
|
} else {
|
|
assert(0 && "Unknown regclass!");
|
|
abort();
|
|
}
|
|
}
|
|
|
|
void
|
|
PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
unsigned DestReg, int FrameIdx,
|
|
const TargetRegisterClass *RC) const {
|
|
MachineFunction &MF = *MBB.getParent();
|
|
SmallVector<MachineInstr*, 4> NewMIs;
|
|
LoadRegFromStackSlot(MF, DestReg, FrameIdx, RC, NewMIs);
|
|
for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
|
|
MBB.insert(MI, NewMIs[i]);
|
|
}
|
|
|
|
void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
|
SmallVectorImpl<MachineOperand> &Addr,
|
|
const TargetRegisterClass *RC,
|
|
SmallVectorImpl<MachineInstr*> &NewMIs)const{
|
|
if (Addr[0].isFI()) {
|
|
LoadRegFromStackSlot(MF, DestReg, Addr[0].getIndex(), RC, NewMIs);
|
|
return;
|
|
}
|
|
|
|
unsigned Opc = 0;
|
|
if (RC == PPC::GPRCRegisterClass) {
|
|
assert(DestReg != PPC::LR && "Can't handle this yet!");
|
|
Opc = PPC::LWZ;
|
|
} else if (RC == PPC::G8RCRegisterClass) {
|
|
assert(DestReg != PPC::LR8 && "Can't handle this yet!");
|
|
Opc = PPC::LD;
|
|
} else if (RC == PPC::F8RCRegisterClass) {
|
|
Opc = PPC::LFD;
|
|
} else if (RC == PPC::F4RCRegisterClass) {
|
|
Opc = PPC::LFS;
|
|
} else if (RC == PPC::VRRCRegisterClass) {
|
|
Opc = PPC::LVX;
|
|
} else {
|
|
assert(0 && "Unknown regclass!");
|
|
abort();
|
|
}
|
|
MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
|
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
|
|
MachineOperand &MO = Addr[i];
|
|
if (MO.isReg())
|
|
MIB.addReg(MO.getReg());
|
|
else if (MO.isImm())
|
|
MIB.addImm(MO.getImm());
|
|
else
|
|
MIB.addFrameIndex(MO.getIndex());
|
|
}
|
|
NewMIs.push_back(MIB);
|
|
return;
|
|
}
|
|
|
|
/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
|
|
/// copy instructions, turning them into load/store instructions.
|
|
MachineInstr *PPCInstrInfo::foldMemoryOperand(MachineFunction &MF,
|
|
MachineInstr *MI,
|
|
const SmallVectorImpl<unsigned> &Ops,
|
|
int FrameIndex) const {
|
|
if (Ops.size() != 1) return NULL;
|
|
|
|
// Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
|
|
// it takes more than one instruction to store it.
|
|
unsigned Opc = MI->getOpcode();
|
|
unsigned OpNum = Ops[0];
|
|
|
|
MachineInstr *NewMI = NULL;
|
|
if ((Opc == PPC::OR &&
|
|
MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
|
|
if (OpNum == 0) { // move -> store
|
|
unsigned InReg = MI->getOperand(1).getReg();
|
|
bool isKill = MI->getOperand(1).isKill();
|
|
NewMI = addFrameReference(BuildMI(MF, get(PPC::STW))
|
|
.addReg(InReg, false, false, isKill),
|
|
FrameIndex);
|
|
} else { // move -> load
|
|
unsigned OutReg = MI->getOperand(0).getReg();
|
|
bool isDead = MI->getOperand(0).isDead();
|
|
NewMI = addFrameReference(BuildMI(MF, get(PPC::LWZ))
|
|
.addReg(OutReg, true, false, false, isDead),
|
|
FrameIndex);
|
|
}
|
|
} else if ((Opc == PPC::OR8 &&
|
|
MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
|
|
if (OpNum == 0) { // move -> store
|
|
unsigned InReg = MI->getOperand(1).getReg();
|
|
bool isKill = MI->getOperand(1).isKill();
|
|
NewMI = addFrameReference(BuildMI(MF, get(PPC::STD))
|
|
.addReg(InReg, false, false, isKill),
|
|
FrameIndex);
|
|
} else { // move -> load
|
|
unsigned OutReg = MI->getOperand(0).getReg();
|
|
bool isDead = MI->getOperand(0).isDead();
|
|
NewMI = addFrameReference(BuildMI(MF, get(PPC::LD))
|
|
.addReg(OutReg, true, false, false, isDead),
|
|
FrameIndex);
|
|
}
|
|
} else if (Opc == PPC::FMRD) {
|
|
if (OpNum == 0) { // move -> store
|
|
unsigned InReg = MI->getOperand(1).getReg();
|
|
bool isKill = MI->getOperand(1).isKill();
|
|
NewMI = addFrameReference(BuildMI(MF, get(PPC::STFD))
|
|
.addReg(InReg, false, false, isKill),
|
|
FrameIndex);
|
|
} else { // move -> load
|
|
unsigned OutReg = MI->getOperand(0).getReg();
|
|
bool isDead = MI->getOperand(0).isDead();
|
|
NewMI = addFrameReference(BuildMI(MF, get(PPC::LFD))
|
|
.addReg(OutReg, true, false, false, isDead),
|
|
FrameIndex);
|
|
}
|
|
} else if (Opc == PPC::FMRS) {
|
|
if (OpNum == 0) { // move -> store
|
|
unsigned InReg = MI->getOperand(1).getReg();
|
|
bool isKill = MI->getOperand(1).isKill();
|
|
NewMI = addFrameReference(BuildMI(MF, get(PPC::STFS))
|
|
.addReg(InReg, false, false, isKill),
|
|
FrameIndex);
|
|
} else { // move -> load
|
|
unsigned OutReg = MI->getOperand(0).getReg();
|
|
bool isDead = MI->getOperand(0).isDead();
|
|
NewMI = addFrameReference(BuildMI(MF, get(PPC::LFS))
|
|
.addReg(OutReg, true, false, false, isDead),
|
|
FrameIndex);
|
|
}
|
|
}
|
|
|
|
return NewMI;
|
|
}
|
|
|
|
bool PPCInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
|
|
const SmallVectorImpl<unsigned> &Ops) const {
|
|
if (Ops.size() != 1) return false;
|
|
|
|
// Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
|
|
// it takes more than one instruction to store it.
|
|
unsigned Opc = MI->getOpcode();
|
|
|
|
if ((Opc == PPC::OR &&
|
|
MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
|
|
return true;
|
|
else if ((Opc == PPC::OR8 &&
|
|
MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
|
|
return true;
|
|
else if (Opc == PPC::FMRD || Opc == PPC::FMRS)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
|
|
bool PPCInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
|
|
if (MBB.empty()) return false;
|
|
|
|
switch (MBB.back().getOpcode()) {
|
|
case PPC::BLR: // Return.
|
|
case PPC::B: // Uncond branch.
|
|
case PPC::BCTR: // Indirect branch.
|
|
return true;
|
|
default: return false;
|
|
}
|
|
}
|
|
|
|
bool PPCInstrInfo::
|
|
ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
|
|
assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
|
|
// Leave the CR# the same, but invert the condition.
|
|
Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
|
|
return false;
|
|
}
|
|
|
|
/// GetInstSize - Return the number of bytes of code the specified
|
|
/// instruction may be. This returns the maximum number of bytes.
|
|
///
|
|
unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
|
|
switch (MI->getOpcode()) {
|
|
case PPC::INLINEASM: { // Inline Asm: Variable size.
|
|
const MachineFunction *MF = MI->getParent()->getParent();
|
|
const char *AsmStr = MI->getOperand(0).getSymbolName();
|
|
return MF->getTarget().getTargetAsmInfo()->getInlineAsmLength(AsmStr);
|
|
}
|
|
case PPC::DBG_LABEL:
|
|
case PPC::EH_LABEL:
|
|
case PPC::GC_LABEL:
|
|
return 0;
|
|
default:
|
|
return 4; // PowerPC instructions are all 4 bytes
|
|
}
|
|
}
|