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5ce227e787
- Use static allocation for aligned stack objects. - Simplify dynamic stack object allocation. - Simplify elimination of frame-indices. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235521 91177308-0d34-0410-b5e6-96231b3b80d8
86 lines
2.9 KiB
C++
86 lines
2.9 KiB
C++
//=- HexagonMachineFunctionInfo.h - Hexagon machine function info -*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H
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#include "llvm/CodeGen/MachineFunction.h"
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#include <map>
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namespace llvm {
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namespace Hexagon {
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const unsigned int StartPacket = 0x1;
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const unsigned int EndPacket = 0x2;
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}
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/// Hexagon target-specific information for each MachineFunction.
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class HexagonMachineFunctionInfo : public MachineFunctionInfo {
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// SRetReturnReg - Some subtargets require that sret lowering includes
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// returning the value of the returned struct in a register. This field
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// holds the virtual register into which the sret argument is passed.
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unsigned SRetReturnReg;
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unsigned StackAlignBaseReg;
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std::vector<MachineInstr*> AllocaAdjustInsts;
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int VarArgsFrameIndex;
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bool HasClobberLR;
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bool HasEHReturn;
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std::map<const MachineInstr*, unsigned> PacketInfo;
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virtual void anchor();
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public:
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HexagonMachineFunctionInfo() : SRetReturnReg(0), StackAlignBaseReg(0),
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HasClobberLR(0), HasEHReturn(false) {}
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HexagonMachineFunctionInfo(MachineFunction &MF) : SRetReturnReg(0),
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StackAlignBaseReg(0),
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HasClobberLR(0),
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HasEHReturn(false) {}
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unsigned getSRetReturnReg() const { return SRetReturnReg; }
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void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
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void addAllocaAdjustInst(MachineInstr* MI) {
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AllocaAdjustInsts.push_back(MI);
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}
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const std::vector<MachineInstr*>& getAllocaAdjustInsts() {
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return AllocaAdjustInsts;
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}
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void setVarArgsFrameIndex(int v) { VarArgsFrameIndex = v; }
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int getVarArgsFrameIndex() { return VarArgsFrameIndex; }
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void setStartPacket(MachineInstr* MI) {
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PacketInfo[MI] |= Hexagon::StartPacket;
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}
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void setEndPacket(MachineInstr* MI) {
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PacketInfo[MI] |= Hexagon::EndPacket;
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}
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bool isStartPacket(const MachineInstr* MI) const {
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return (PacketInfo.count(MI) &&
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(PacketInfo.find(MI)->second & Hexagon::StartPacket));
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}
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bool isEndPacket(const MachineInstr* MI) const {
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return (PacketInfo.count(MI) &&
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(PacketInfo.find(MI)->second & Hexagon::EndPacket));
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}
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void setHasClobberLR(bool v) { HasClobberLR = v; }
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bool hasClobberLR() const { return HasClobberLR; }
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bool hasEHReturn() const { return HasEHReturn; };
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void setHasEHReturn(bool H = true) { HasEHReturn = H; };
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void setStackAlignBaseVReg(unsigned R) { StackAlignBaseReg = R; }
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unsigned getStackAlignBaseVReg() const { return StackAlignBaseReg; }
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};
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} // End llvm namespace
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#endif
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