Richard Sandiford fa487e83a8 [SystemZ] Fold more spills ... Add a mapping from register-based <INSN>R instructions to the corresponding memory-based <INSN>. Use it to cut down on the number of spill loads. Some instructions extend their operands from smaller fields, so this required a new TSFlags field to say how big the unextended operand is. This optimisation doesn't trigger for C(G)R and CL(G)R because in practice we always combine those instructions with a branch. Adding a test for every other case probably seems excessive, but it did catch a missed optimisation for DSGF (fixed in r185435). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185529 91177308-0d34-0410-b5e6-96231b3b80d8		2013-07-03 10:10:02 +00:00
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AArch64	AArch64: correct CodeGen of MOVZ/MOVK combinations.	2013-07-01 19:23:10 +00:00
ARM	ARM: relax the atomic release barrier to "dmb ishst" on Swift	2013-07-03 09:20:36 +00:00
CPP
Generic
Hexagon
Inputs
MBlaze
Mips	[mips] Fix test case to check that mips64 instructions are generated.	2013-07-01 20:18:58 +00:00
MSP430	Really fix the test. Sorry for the breakage...	2013-07-01 19:51:36 +00:00
NVPTX	[NVPTX] Add support for module-scope inline asm	2013-07-01 13:00:14 +00:00
PowerPC	[PowerPC] Remove VK_PPC_TLSGD and VK_PPC_TLSLD	2013-07-02 21:29:06 +00:00
R600	R600: Support schedule and packetization of trans-only inst	2013-06-29 19:32:43 +00:00
SI
SPARC
SystemZ	[SystemZ] Fold more spills	2013-07-03 10:10:02 +00:00
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X86	DAGCombiner: fix use-counting issue when forming zextload	2013-07-02 09:58:53 +00:00
XCore	[XCore] Add ISel pattern for LDWCP	2013-07-03 07:48:50 +00:00