mirror of
https://github.com/c64scene-ar/llvm-6502.git
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b00cd1c899
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95654 91177308-0d34-0410-b5e6-96231b3b80d8
95 lines
2.1 KiB
LLVM
95 lines
2.1 KiB
LLVM
; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X32
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; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=X64
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; The immediate can be encoded in a smaller way if the
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; instruction is a sub instead of an add.
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define i32 @test1(i32 inreg %a) nounwind {
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%b = add i32 %a, 128
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ret i32 %b
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; X32: subl $-128, %eax
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; X64: subl $-128,
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}
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define i64 @test2(i64 inreg %a) nounwind {
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%b = add i64 %a, 2147483648
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ret i64 %b
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; X32: addl $-2147483648, %eax
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; X64: subq $-2147483648,
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}
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define i64 @test3(i64 inreg %a) nounwind {
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%b = add i64 %a, 128
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ret i64 %b
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; X32: addl $128, %eax
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; X64: subq $-128,
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}
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define i1 @test4(i32 %v1, i32 %v2, i32* %X) nounwind {
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entry:
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%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
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%sum = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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br i1 %obit, label %overflow, label %normal
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normal:
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store i32 0, i32* %X
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br label %overflow
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overflow:
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ret i1 false
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; X32: test4:
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; X32: addl
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; X32-NEXT: jo
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; X64: test4:
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; X64: addl %esi, %edi
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; X64-NEXT: jo
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}
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define i1 @test5(i32 %v1, i32 %v2, i32* %X) nounwind {
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entry:
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%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
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%sum = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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br i1 %obit, label %carry, label %normal
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normal:
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store i32 0, i32* %X
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br label %carry
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carry:
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ret i1 false
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; X32: test5:
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; X32: addl
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; X32-NEXT: jb
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; X64: test5:
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; X64: addl %esi, %edi
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; X64-NEXT: jb
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}
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declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32)
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declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32)
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define i64 @test6(i64 %A, i32 %B) nounwind {
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%tmp12 = zext i32 %B to i64 ; <i64> [#uses=1]
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%tmp3 = shl i64 %tmp12, 32 ; <i64> [#uses=1]
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%tmp5 = add i64 %tmp3, %A ; <i64> [#uses=1]
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ret i64 %tmp5
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; X32: test6:
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; X32: movl 12(%esp), %edx
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; X32-NEXT: addl 8(%esp), %edx
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; X32-NEXT: movl 4(%esp), %eax
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; X32-NEXT: ret
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; X64: test6:
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; X64: shlq $32, %rsi
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; X64: leaq (%rsi,%rdi), %rax
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; X64: ret
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}
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