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	This fixes PR7540. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107809 91177308-0d34-0410-b5e6-96231b3b80d8
		
			
				
	
	
		
			144 lines
		
	
	
		
			5.0 KiB
		
	
	
	
		
			LLVM
		
	
	
	
	
	
			
		
		
	
	
			144 lines
		
	
	
		
			5.0 KiB
		
	
	
	
		
			LLVM
		
	
	
	
	
	
| ; RUN: llc -march=x86 %s -o -
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| ; RUN: llc -march=x86-64 %s -o -
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| 
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| ; PR6497
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| 
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| ; Chain and flag folding issues.
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| define i32 @test1() nounwind ssp {
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| entry:
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|   %tmp5.i = volatile load i32* undef              ; <i32> [#uses=1]
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|   %conv.i = zext i32 %tmp5.i to i64               ; <i64> [#uses=1]
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|   %tmp12.i = volatile load i32* undef             ; <i32> [#uses=1]
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|   %conv13.i = zext i32 %tmp12.i to i64            ; <i64> [#uses=1]
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|   %shl.i = shl i64 %conv13.i, 32                  ; <i64> [#uses=1]
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|   %or.i = or i64 %shl.i, %conv.i                  ; <i64> [#uses=1]
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|   %add16.i = add i64 %or.i, 256                   ; <i64> [#uses=1]
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|   %shr.i = lshr i64 %add16.i, 8                   ; <i64> [#uses=1]
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|   %conv19.i = trunc i64 %shr.i to i32             ; <i32> [#uses=1]
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|   volatile store i32 %conv19.i, i32* undef
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|   ret i32 undef
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| }
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| 
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| ; PR6533
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| define void @test2(i1 %x, i32 %y) nounwind {
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|   %land.ext = zext i1 %x to i32                   ; <i32> [#uses=1]
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|   %and = and i32 %y, 1                        ; <i32> [#uses=1]
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|   %xor = xor i32 %and, %land.ext                  ; <i32> [#uses=1]
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|   %cmp = icmp eq i32 %xor, 1                      ; <i1> [#uses=1]
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|   br i1 %cmp, label %if.end, label %if.then
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| 
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| if.then:                                          ; preds = %land.end
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|   ret void
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| 
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| if.end:                                           ; preds = %land.end
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|   ret void
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| }
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| 
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| ; PR6577
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| %pair = type { i64, double }
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| 
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| define void @test3() {
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| dependentGraph243.exit:
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|   %subject19 = load %pair* undef                     ; <%1> [#uses=1]
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|   %0 = extractvalue %pair %subject19, 1              ; <double> [#uses=2]
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|   %1 = select i1 undef, double %0, double undef   ; <double> [#uses=1]
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|   %2 = select i1 undef, double %1, double %0      ; <double> [#uses=1]
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|   %3 = insertvalue %pair undef, double %2, 1         ; <%1> [#uses=1]
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|   store %pair %3, %pair* undef
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|   ret void
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| }
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| 
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| ; PR6605
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| define i64 @test4(i8* %P) nounwind ssp {
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| entry:
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|   %tmp1 = load i8* %P                           ; <i8> [#uses=3]
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|   %tobool = icmp eq i8 %tmp1, 0                   ; <i1> [#uses=1]
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|   %tmp58 = sext i1 %tobool to i8                  ; <i8> [#uses=1]
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|   %mul.i = and i8 %tmp58, %tmp1                   ; <i8> [#uses=1]
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|   %conv6 = zext i8 %mul.i to i32                  ; <i32> [#uses=1]
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|   %cmp = icmp ne i8 %tmp1, 1                      ; <i1> [#uses=1]
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|   %conv11 = zext i1 %cmp to i32                   ; <i32> [#uses=1]
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|   %call12 = tail call i32 @safe(i32 %conv11) nounwind ; <i32> [#uses=1]
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|   %and = and i32 %conv6, %call12                  ; <i32> [#uses=1]
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|   %tobool13 = icmp eq i32 %and, 0                 ; <i1> [#uses=1]
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|   br i1 %tobool13, label %if.else, label %return
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| 
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| if.else:                                          ; preds = %entry
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|   br label %return
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| 
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| return:                                           ; preds = %if.else, %entry
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|   ret i64 undef
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| }
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| 
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| declare i32 @safe(i32)
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| 
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| ; PR6607
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| define fastcc void @test5(i32 %FUNC) nounwind {
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| foo:
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|   %0 = load i8* undef, align 1                    ; <i8> [#uses=3]
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|   %1 = sext i8 %0 to i32                          ; <i32> [#uses=2]
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|   %2 = zext i8 %0 to i32                          ; <i32> [#uses=1]
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|   %tmp1.i5037 = urem i32 %2, 10                   ; <i32> [#uses=1]
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|   %tmp.i5038 = icmp ugt i32 %tmp1.i5037, 15       ; <i1> [#uses=1]
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|   %3 = zext i1 %tmp.i5038 to i8                   ; <i8> [#uses=1]
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|   %4 = icmp slt i8 %0, %3                         ; <i1> [#uses=1]
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|   %5 = add nsw i32 %1, 256                        ; <i32> [#uses=1]
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|   %storemerge.i.i57 = select i1 %4, i32 %5, i32 %1 ; <i32> [#uses=1]
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|   %6 = shl i32 %storemerge.i.i57, 16              ; <i32> [#uses=1]
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|   %7 = sdiv i32 %6, -256                          ; <i32> [#uses=1]
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|   %8 = trunc i32 %7 to i8                         ; <i8> [#uses=1]
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|   store i8 %8, i8* undef, align 1
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|   ret void
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| }
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| 
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| 
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| ; Crash commoning identical asms.
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| ; PR6803
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| define void @test6(i1 %C) nounwind optsize ssp {
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| entry:
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|   br i1 %C, label %do.body55, label %do.body92
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| 
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| do.body55:                                        ; preds = %if.else36
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|   call void asm sideeffect "foo", "~{dirflag},~{fpsr},~{flags}"() nounwind, !srcloc !0
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|   ret void
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| 
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| do.body92:                                        ; preds = %if.then66
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|   call void asm sideeffect "foo", "~{dirflag},~{fpsr},~{flags}"() nounwind, !srcloc !1
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|   ret void
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| }
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| 
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| !0 = metadata !{i32 633550}                       
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| !1 = metadata !{i32 634261}                       
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| 
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| 
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| ; Crash during XOR optimization.
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| ; <rdar://problem/7869290>
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| 
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| define void @test7() nounwind ssp {
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| entry:
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|   br i1 undef, label %bb14, label %bb67
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| 
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| bb14:
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|   %tmp0 = trunc i16 undef to i1
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|   %tmp1 = load i8* undef, align 8
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|   %tmp2 = shl i8 %tmp1, 4
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|   %tmp3 = lshr i8 %tmp2, 7
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|   %tmp4 = trunc i8 %tmp3 to i1
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|   %tmp5 = icmp ne i1 %tmp0, %tmp4
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|   br i1 %tmp5, label %bb14, label %bb67
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| 
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| bb67:
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|   ret void
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| }
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| 
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| ; Crash when trying to copy AH to AL.
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| ; PR7540
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| define void @copy8bitregs() nounwind {
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| entry:
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|   %div.i = sdiv i32 115200, 0
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|   %shr8.i = lshr i32 %div.i, 8
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|   %conv4.i = trunc i32 %shr8.i to i8
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|   call void asm sideeffect "outb $0, ${1:w}", "{ax},N{dx},~{dirflag},~{fpsr},~{flags}"(i8 %conv4.i, i32 1017) nounwind
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|   unreachable
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| }
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