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584fedf188
opportunities. For example, this lets it emit this: movq (%rax), %rcx addq %rdx, %rcx instead of this: movq %rdx, %rcx addq (%rax), %rcx in the case where %rdx has subsequent uses. It's the same number of instructions, and usually the same encoding size on x86, but it appears faster, and in general, it may allow better scheduling for the load. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106493 91177308-0d34-0410-b5e6-96231b3b80d8
26 lines
989 B
LLVM
26 lines
989 B
LLVM
; RUN: llc < %s -tailcallopt -march=x86-64 -post-RA-scheduler=true | FileCheck %s
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; Check that lowered arguments on the stack do not overwrite each other.
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; Add %in1 %p1 to a different temporary register (%eax).
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; CHECK: movl 32(%rsp), %eax
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; Move param %in1 to temp register (%r10d).
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; CHECK: movl 40(%rsp), %r10d
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; Add %in1 %p1 to a different temporary register (%eax).
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; CHECK: addl %edi, %eax
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; Move param %in2 to stack.
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; CHECK: movl %r10d, 32(%rsp)
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; Move result of addition to stack.
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; CHECK: movl %eax, 40(%rsp)
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; Eventually, do a TAILCALL
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; CHECK: TAILCALL
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declare fastcc i32 @tailcallee(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %a, i32 %b) nounwind
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define fastcc i32 @tailcaller(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %in1, i32 %in2) nounwind {
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entry:
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%tmp = add i32 %in1, %p1
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%retval = tail call fastcc i32 @tailcallee(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %in2,i32 %tmp)
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ret i32 %retval
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}
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