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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22867 91177308-0d34-0410-b5e6-96231b3b80d8
73 lines
2.3 KiB
C++
73 lines
2.3 KiB
C++
//===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the SelectionDAGISel class, which is used as the common
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// base class for SelectionDAG-based instruction selectors.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
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#define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
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#include "llvm/Pass.h"
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#include "llvm/CodeGen/ValueTypes.h"
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namespace llvm {
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class SelectionDAG;
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class SelectionDAGLowering;
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class SDOperand;
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class SSARegMap;
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class MachineBasicBlock;
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class MachineFunction;
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class MachineInstr;
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class TargetLowering;
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class FunctionLoweringInfo;
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/// SelectionDAGISel - This is the common base class used for SelectionDAG-based
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/// pattern-matching instruction selectors.
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class SelectionDAGISel : public FunctionPass {
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public:
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TargetLowering &TLI;
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SSARegMap *RegMap;
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SelectionDAG *CurDAG;
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MachineBasicBlock *BB;
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SelectionDAGISel(TargetLowering &tli) : TLI(tli) {}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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virtual bool runOnFunction(Function &Fn);
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unsigned MakeReg(MVT::ValueType VT);
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virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
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virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0;
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protected:
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/// Pick a safe ordering and emit instructions for each target node in the
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/// graph.
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void ScheduleAndEmitDAG(SelectionDAG &SD);
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private:
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SDOperand CopyValueToVirtualRegister(SelectionDAGLowering &SDL,
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Value *V, unsigned Reg);
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void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF,
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FunctionLoweringInfo &FuncInfo);
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void BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
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std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
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FunctionLoweringInfo &FuncInfo);
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void LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
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std::vector<SDOperand> &UnorderedChains);
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};
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}
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#endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */
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