Patrik Hägglund d5f03186e5 Cleanup: Simplify loop end logic in computeRegisterProperties(). ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168507 91177308-0d34-0410-b5e6-96231b3b80d8

2012-11-23 08:35:04 +00:00

..

CMakeLists.txt

llvm/lib: [CMake] Add explicit dependency to intrinsics_gen.

2012-06-24 13:32:01 +00:00

DAGCombiner.cpp

Handle DAG CSE adding new uses during ReplaceAllUsesWith. Fixes PR14333.

2012-11-14 05:08:56 +00:00

FastISel.cpp

Revert the series of commits starting with r166578 which introduced the

2012-11-01 08:07:29 +00:00

FunctionLoweringInfo.cpp

Move TargetData to DataLayout.

2012-10-08 16:38:25 +00:00

InstrEmitter.cpp

[inline asm] Get the mayLoad/mayStore directly from the MIOp_ExtraInfo operand.

2012-10-30 20:39:19 +00:00

InstrEmitter.h

Allow trailing physreg RegisterSDNode operands on non-variadic instructions.

2012-07-04 23:53:23 +00:00

LegalizeDAG.cpp

Back out r166591, not sure why this made it through since I cancelled the command. Bleh, sorry about this!

2012-10-24 17:25:11 +00:00

LegalizeFloatTypes.cpp

Follow the same routine to add target float expansion hook

2012-10-11 07:22:01 +00:00

LegalizeIntegerTypes.cpp

Back out r166591, not sure why this made it through since I cancelled the command. Bleh, sorry about this!

2012-10-24 17:25:11 +00:00

LegalizeTypes.cpp

Move TargetData to DataLayout.

2012-10-08 16:38:25 +00:00

LegalizeTypes.h

Add alternative support for FP_ROUND from v2f32 to v2f64

2012-10-10 16:32:15 +00:00

LegalizeTypesGeneric.cpp

Fix big-endian codegen bug in DAGTypeLegalizer::ExpandRes_BITCAST

2012-10-12 15:42:58 +00:00

LegalizeVectorOps.cpp

Mark FP_EXTEND form v2f32 to v2f64 as "expand" for ARM NEON. Patch by Pete Couperus.

2012-11-17 01:52:46 +00:00

LegalizeVectorTypes.cpp

Add alternative support for FP_ROUND from v2f32 to v2f64

2012-10-10 16:32:15 +00:00

LLVMBuild.txt

LLVMBuild: Remove trailing newline, which irked me.

2011-12-12 19:48:00 +00:00

Makefile

…

ResourcePriorityQueue.cpp

I'm introducing a new machine model to simultaneously allow simple

2012-07-07 04:00:00 +00:00

ScheduleDAGFast.cpp

ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.

2012-11-06 03:13:46 +00:00

ScheduleDAGRRList.cpp

misched: Infrastructure for weak DAG edges.

2012-11-12 19:28:57 +00:00

ScheduleDAGSDNodes.cpp

ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.

2012-11-06 03:13:46 +00:00

ScheduleDAGSDNodes.h

Add a really faster pre-RA scheduler (-pre-RA-sched=linearize). It doesn't use

2012-10-17 19:39:36 +00:00

ScheduleDAGVLIW.cpp

misched: Infrastructure for weak DAG edges.

2012-11-12 19:28:57 +00:00

SDNodeDbgValue.h

…

SDNodeOrdering.h

Mark unimplemented copy constructors and copy assignment operators as LLVM_DELETED_FUNCTION.

2012-09-18 02:01:41 +00:00

SelectionDAG.cpp

Revert the majority of the next patch in the address space series:

2012-11-01 09:14:31 +00:00

SelectionDAGBuilder.cpp

llvm.fmuladd.* lowering should be checking isOperationLegalOrCustom, rather than

2012-11-22 03:31:45 +00:00

SelectionDAGBuilder.h

Move TargetData to DataLayout.

2012-10-08 16:38:25 +00:00

SelectionDAGDumper.cpp

Fix PR11985

2012-09-12 21:43:09 +00:00

SelectionDAGISel.cpp

misched: Allow subtargets to enable misched and dependent options.

2012-11-13 08:47:29 +00:00

SelectionDAGPrinter.cpp

Constify SDNodeIterator an stop its only non-const user being cast stripped

2012-09-05 22:03:34 +00:00

TargetLowering.cpp

Cleanup: Simplify loop end logic in computeRegisterProperties().

2012-11-23 08:35:04 +00:00

TargetSelectionDAGInfo.cpp

Move TargetData to DataLayout.

2012-10-08 16:38:25 +00:00