Evan Cheng d61c4820c9 Make CALL node consistent with RET node. Signness of value has type MVT::i32 ...

instead of MVT::i1. Either is fine except MVT::i32 is probably a legal type
for most (if not all) platforms while MVT::i1 is not.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28511 91177308-0d34-0410-b5e6-96231b3b80d8

2006-05-26 23:13:20 +00:00

..

SelectionDAG

Make CALL node consistent with RET node. Signness of value has type MVT::i32

2006-05-26 23:13:20 +00:00

AsmPrinter.cpp

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BranchFolding.cpp

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DwarfWriter.cpp

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ELFWriter.cpp

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IntrinsicLowering.cpp

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LiveInterval.cpp

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LiveIntervalAnalysis.cpp

Patches to make the LLVM sources more -pedantic clean. Patch provided

2006-05-24 17:04:05 +00:00

LiveVariables.cpp

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MachineBasicBlock.cpp

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MachineDebugInfo.cpp

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MachineFunction.cpp

Print the vreg that livein physregs are live in

2006-05-16 05:55:30 +00:00

MachineInstr.cpp

Remove a bogus cast.

2006-05-26 08:00:14 +00:00

Makefile

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Passes.cpp

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PHIElimination.cpp

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PhysRegTracker.h

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PrologEpilogInserter.cpp

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RegAllocLinearScan.cpp

If the register allocator cannot find a register to spill, try the aliases. If

2006-05-12 19:07:46 +00:00

RegAllocLocal.cpp

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RegAllocSimple.cpp

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TwoAddressInstructionPass.cpp

Patches to make the LLVM sources more -pedantic clean. Patch provided

2006-05-24 17:04:05 +00:00

UnreachableBlockElim.cpp

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VirtRegMap.cpp

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VirtRegMap.h

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