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https://github.com/c64scene-ar/llvm-6502.git
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015408c6b1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224026 91177308-0d34-0410-b5e6-96231b3b80d8
345 lines
12 KiB
C++
345 lines
12 KiB
C++
//===-- HexagonPeephole.cpp - Hexagon Peephole Optimiztions ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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// This peephole pass optimizes in the following cases.
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// 1. Optimizes redundant sign extends for the following case
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// Transform the following pattern
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// %vreg170<def> = SXTW %vreg166
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// ...
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// %vreg176<def> = COPY %vreg170:subreg_loreg
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//
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// Into
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// %vreg176<def> = COPY vreg166
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//
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// 2. Optimizes redundant negation of predicates.
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// %vreg15<def> = CMPGTrr %vreg6, %vreg2
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// ...
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// %vreg16<def> = NOT_p %vreg15<kill>
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// ...
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// JMP_c %vreg16<kill>, <BB#1>, %PC<imp-def,dead>
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//
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// Into
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// %vreg15<def> = CMPGTrr %vreg6, %vreg2;
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// ...
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// JMP_cNot %vreg15<kill>, <BB#1>, %PC<imp-def,dead>;
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//
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// Note: The peephole pass makes the instrucstions like
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// %vreg170<def> = SXTW %vreg166 or %vreg16<def> = NOT_p %vreg15<kill>
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// redundant and relies on some form of dead removal instructions, like
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// DCE or DIE to actually eliminate them.
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//===----------------------------------------------------------------------===//
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#include "Hexagon.h"
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#include "HexagonTargetMachine.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/PassSupport.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include <algorithm>
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using namespace llvm;
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#define DEBUG_TYPE "hexagon-peephole"
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static cl::opt<bool> DisableHexagonPeephole("disable-hexagon-peephole",
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Disable Peephole Optimization"));
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static cl::opt<bool> DisablePNotP("disable-hexagon-pnotp",
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Disable Optimization of PNotP"));
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static cl::opt<bool> DisableOptSZExt("disable-hexagon-optszext",
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Disable Optimization of Sign/Zero Extends"));
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static cl::opt<bool> DisableOptExtTo64("disable-hexagon-opt-ext-to-64",
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Disable Optimization of extensions to i64."));
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namespace llvm {
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void initializeHexagonPeepholePass(PassRegistry&);
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}
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namespace {
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struct HexagonPeephole : public MachineFunctionPass {
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const HexagonInstrInfo *QII;
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const HexagonRegisterInfo *QRI;
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const MachineRegisterInfo *MRI;
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public:
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static char ID;
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HexagonPeephole() : MachineFunctionPass(ID) {
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initializeHexagonPeepholePass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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const char *getPassName() const override {
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return "Hexagon optimize redundant zero and size extends";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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void ChangeOpInto(MachineOperand &Dst, MachineOperand &Src);
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};
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}
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char HexagonPeephole::ID = 0;
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INITIALIZE_PASS(HexagonPeephole, "hexagon-peephole", "Hexagon Peephole",
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false, false)
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bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
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QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
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QRI = MF.getTarget().getSubtarget<HexagonSubtarget>().getRegisterInfo();
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MRI = &MF.getRegInfo();
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DenseMap<unsigned, unsigned> PeepholeMap;
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DenseMap<unsigned, std::pair<unsigned, unsigned> > PeepholeDoubleRegsMap;
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if (DisableHexagonPeephole) return false;
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// Loop over all of the basic blocks.
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for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
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MBBb != MBBe; ++MBBb) {
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MachineBasicBlock* MBB = MBBb;
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PeepholeMap.clear();
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PeepholeDoubleRegsMap.clear();
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// Traverse the basic block.
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for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end();
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++MII) {
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MachineInstr *MI = MII;
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// Look for sign extends:
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// %vreg170<def> = SXTW %vreg166
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if (!DisableOptSZExt && MI->getOpcode() == Hexagon::A2_sxtw) {
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assert (MI->getNumOperands() == 2);
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MachineOperand &Dst = MI->getOperand(0);
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MachineOperand &Src = MI->getOperand(1);
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unsigned DstReg = Dst.getReg();
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unsigned SrcReg = Src.getReg();
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// Just handle virtual registers.
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if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
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TargetRegisterInfo::isVirtualRegister(SrcReg)) {
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// Map the following:
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// %vreg170<def> = SXTW %vreg166
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// PeepholeMap[170] = vreg166
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PeepholeMap[DstReg] = SrcReg;
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}
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}
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// Look for %vreg170<def> = COMBINE_ir_V4 (0, %vreg169)
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// %vreg170:DoublRegs, %vreg169:IntRegs
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if (!DisableOptExtTo64 &&
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MI->getOpcode () == Hexagon::COMBINE_Ir_V4) {
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assert (MI->getNumOperands() == 3);
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MachineOperand &Dst = MI->getOperand(0);
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MachineOperand &Src1 = MI->getOperand(1);
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MachineOperand &Src2 = MI->getOperand(2);
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if (Src1.getImm() != 0)
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continue;
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unsigned DstReg = Dst.getReg();
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unsigned SrcReg = Src2.getReg();
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PeepholeMap[DstReg] = SrcReg;
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}
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// Look for this sequence below
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// %vregDoubleReg1 = LSRd_ri %vregDoubleReg0, 32
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// %vregIntReg = COPY %vregDoubleReg1:subreg_loreg.
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// and convert into
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// %vregIntReg = COPY %vregDoubleReg0:subreg_hireg.
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if (MI->getOpcode() == Hexagon::LSRd_ri) {
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assert(MI->getNumOperands() == 3);
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MachineOperand &Dst = MI->getOperand(0);
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MachineOperand &Src1 = MI->getOperand(1);
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MachineOperand &Src2 = MI->getOperand(2);
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if (Src2.getImm() != 32)
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continue;
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unsigned DstReg = Dst.getReg();
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unsigned SrcReg = Src1.getReg();
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PeepholeDoubleRegsMap[DstReg] =
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std::make_pair(*&SrcReg, 1/*Hexagon::subreg_hireg*/);
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}
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// Look for P=NOT(P).
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if (!DisablePNotP &&
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(MI->getOpcode() == Hexagon::C2_not)) {
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assert (MI->getNumOperands() == 2);
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MachineOperand &Dst = MI->getOperand(0);
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MachineOperand &Src = MI->getOperand(1);
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unsigned DstReg = Dst.getReg();
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unsigned SrcReg = Src.getReg();
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// Just handle virtual registers.
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if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
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TargetRegisterInfo::isVirtualRegister(SrcReg)) {
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// Map the following:
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// %vreg170<def> = NOT_xx %vreg166
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// PeepholeMap[170] = vreg166
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PeepholeMap[DstReg] = SrcReg;
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}
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}
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// Look for copy:
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// %vreg176<def> = COPY %vreg170:subreg_loreg
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if (!DisableOptSZExt && MI->isCopy()) {
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assert (MI->getNumOperands() == 2);
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MachineOperand &Dst = MI->getOperand(0);
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MachineOperand &Src = MI->getOperand(1);
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// Make sure we are copying the lower 32 bits.
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if (Src.getSubReg() != Hexagon::subreg_loreg)
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continue;
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unsigned DstReg = Dst.getReg();
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unsigned SrcReg = Src.getReg();
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if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
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TargetRegisterInfo::isVirtualRegister(SrcReg)) {
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// Try to find in the map.
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if (unsigned PeepholeSrc = PeepholeMap.lookup(SrcReg)) {
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// Change the 1st operand.
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MI->RemoveOperand(1);
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MI->addOperand(MachineOperand::CreateReg(PeepholeSrc, false));
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} else {
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DenseMap<unsigned, std::pair<unsigned, unsigned> >::iterator DI =
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PeepholeDoubleRegsMap.find(SrcReg);
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if (DI != PeepholeDoubleRegsMap.end()) {
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std::pair<unsigned,unsigned> PeepholeSrc = DI->second;
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MI->RemoveOperand(1);
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MI->addOperand(MachineOperand::CreateReg(PeepholeSrc.first,
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false /*isDef*/,
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false /*isImp*/,
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false /*isKill*/,
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false /*isDead*/,
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false /*isUndef*/,
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false /*isEarlyClobber*/,
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PeepholeSrc.second));
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}
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}
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}
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}
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// Look for Predicated instructions.
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if (!DisablePNotP) {
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bool Done = false;
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if (QII->isPredicated(MI)) {
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MachineOperand &Op0 = MI->getOperand(0);
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unsigned Reg0 = Op0.getReg();
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const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
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if (RC0->getID() == Hexagon::PredRegsRegClassID) {
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// Handle instructions that have a prediate register in op0
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// (most cases of predicable instructions).
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if (TargetRegisterInfo::isVirtualRegister(Reg0)) {
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// Try to find in the map.
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if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {
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// Change the 1st operand and, flip the opcode.
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MI->getOperand(0).setReg(PeepholeSrc);
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int NewOp = QII->getInvertedPredicatedOpcode(MI->getOpcode());
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MI->setDesc(QII->get(NewOp));
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Done = true;
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}
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}
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}
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}
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if (!Done) {
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// Handle special instructions.
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unsigned Op = MI->getOpcode();
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unsigned NewOp = 0;
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unsigned PR = 1, S1 = 2, S2 = 3; // Operand indices.
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switch (Op) {
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case Hexagon::C2_mux:
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case Hexagon::C2_muxii:
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case Hexagon::TFR_condset_ii:
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NewOp = Op;
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break;
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case Hexagon::TFR_condset_ri:
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NewOp = Hexagon::TFR_condset_ir;
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break;
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case Hexagon::TFR_condset_ir:
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NewOp = Hexagon::TFR_condset_ri;
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break;
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case Hexagon::C2_muxri:
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NewOp = Hexagon::C2_muxir;
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break;
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case Hexagon::C2_muxir:
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NewOp = Hexagon::C2_muxri;
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break;
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}
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if (NewOp) {
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unsigned PSrc = MI->getOperand(PR).getReg();
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if (unsigned POrig = PeepholeMap.lookup(PSrc)) {
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MI->getOperand(PR).setReg(POrig);
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MI->setDesc(QII->get(NewOp));
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// Swap operands S1 and S2.
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MachineOperand Op1 = MI->getOperand(S1);
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MachineOperand Op2 = MI->getOperand(S2);
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ChangeOpInto(MI->getOperand(S1), Op2);
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ChangeOpInto(MI->getOperand(S2), Op1);
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}
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} // if (NewOp)
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} // if (!Done)
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} // if (!DisablePNotP)
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} // Instruction
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} // Basic Block
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return true;
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}
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void HexagonPeephole::ChangeOpInto(MachineOperand &Dst, MachineOperand &Src) {
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assert (&Dst != &Src && "Cannot duplicate into itself");
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switch (Dst.getType()) {
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case MachineOperand::MO_Register:
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if (Src.isReg()) {
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Dst.setReg(Src.getReg());
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} else if (Src.isImm()) {
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Dst.ChangeToImmediate(Src.getImm());
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} else {
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llvm_unreachable("Unexpected src operand type");
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}
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break;
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case MachineOperand::MO_Immediate:
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if (Src.isImm()) {
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Dst.setImm(Src.getImm());
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} else if (Src.isReg()) {
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Dst.ChangeToRegister(Src.getReg(), Src.isDef(), Src.isImplicit(),
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Src.isKill(), Src.isDead(), Src.isUndef(),
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Src.isDebug());
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} else {
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llvm_unreachable("Unexpected src operand type");
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}
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break;
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default:
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llvm_unreachable("Unexpected dst operand type");
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break;
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}
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}
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FunctionPass *llvm::createHexagonPeephole() {
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return new HexagonPeephole();
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}
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