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https://github.com/c64scene-ar/llvm-6502.git
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38d3e4d5d8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221210 91177308-0d34-0410-b5e6-96231b3b80d8
89 lines
3.4 KiB
C++
89 lines
3.4 KiB
C++
//===-- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "Hexagon.h"
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#include "MCTargetDesc/HexagonBaseInfo.h"
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#include "MCTargetDesc/HexagonMCCodeEmitter.h"
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#include "MCTargetDesc/HexagonMCTargetDesc.h"
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#include "MCTargetDesc/HexagonMCInst.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#define DEBUG_TYPE "mccodeemitter"
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using namespace llvm;
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using namespace Hexagon;
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STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
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namespace {
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/// \brief 10.6 Instruction Packets
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/// Possible values for instruction packet parse field.
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enum class ParseField { duplex = 0x0, last0 = 0x1, last1 = 0x2, end = 0x3 };
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/// \brief Returns the packet bits based on instruction position.
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uint32_t getPacketBits(HexagonMCInst const &HMI) {
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unsigned const ParseFieldOffset = 14;
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ParseField Field = HMI.isPacketEnd() ? ParseField::end : ParseField::last0;
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return static_cast <uint32_t> (Field) << ParseFieldOffset;
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}
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void emitLittleEndian(uint64_t Binary, raw_ostream &OS) {
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OS << static_cast<uint8_t>((Binary >> 0x00) & 0xff);
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OS << static_cast<uint8_t>((Binary >> 0x08) & 0xff);
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OS << static_cast<uint8_t>((Binary >> 0x10) & 0xff);
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OS << static_cast<uint8_t>((Binary >> 0x18) & 0xff);
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}
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}
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HexagonMCCodeEmitter::HexagonMCCodeEmitter(MCInstrInfo const &aMII,
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MCSubtargetInfo const &aMST,
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MCContext &aMCT)
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: MST(aMST), MCT(aMCT) {}
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void HexagonMCCodeEmitter::EncodeInstruction(MCInst const &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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MCSubtargetInfo const &STI) const {
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HexagonMCInst const &HMB = static_cast<HexagonMCInst const &>(MI);
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uint64_t Binary = getBinaryCodeForInstr(HMB, Fixups, STI) | getPacketBits(HMB);
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assert(HMB.getDesc().getSize() == 4 && "All instructions should be 32bit");
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emitLittleEndian(Binary, OS);
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++MCNumEmitted;
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}
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unsigned
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HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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MCSubtargetInfo const &STI) const {
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if (MO.isReg())
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return MCT.getRegisterInfo()->getEncodingValue(MO.getReg());
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if (MO.isImm())
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return static_cast<unsigned>(MO.getImm());
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llvm_unreachable("Only Immediates and Registers implemented right now");
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}
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MCSubtargetInfo const &HexagonMCCodeEmitter::getSubtargetInfo() const {
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return MST;
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}
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MCCodeEmitter *llvm::createHexagonMCCodeEmitter(MCInstrInfo const &MII,
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MCRegisterInfo const &MRI,
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MCSubtargetInfo const &MST,
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MCContext &MCT) {
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return new HexagonMCCodeEmitter(MII, MST, MCT);
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}
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#include "HexagonGenMCCodeEmitter.inc"
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