llvm-6502/test/CodeGen/CellSPU
Scott Michel 7ea02ffe91 CellSPU:
- Fix fabs, fneg for f32 and f64.
- Use BuildVectorSDNode.isConstantSplat, now that the functionality exists
- Continue to improve i64 constant lowering. Lower certain special constants
  to the constant pool when they correspond to SPU's shufb instruction's
  special mask values. This avoids the overhead of performing a shuffle on a
  zero-filled vector just to get the special constant when the memory load
  suffices.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67067 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-17 01:15:45 +00:00
..
useful-harnesses
2009-01-01-BrCond.ll
and_ops.ll
call_indirect.ll
call.ll
ctpop.ll
dg.exp
dp_farith.ll
eqv.ll
extract_elt.ll
fcmp32.ll
fcmp64.ll
fdiv.ll
fneg-fabs.ll
i8ops.ll
i64ops.ll
icmp8.ll
icmp16.ll
icmp32.ll
icmp64.ll
immed16.ll
immed32.ll
immed64.ll
int2fp.ll
intrinsics_branch.ll
intrinsics_float.ll
intrinsics_logical.ll
loads.ll
mul_ops.ll
nand.ll
or_ops.ll
private.ll
rotate_ops.ll
select_bits.ll
shift_ops.ll
sp_farith.ll
stores.ll
struct_1.ll
trunc.ll
vec_const.ll
vecinsert.ll