David Woodhouse d7ae82f8f5 [x86] Disambiguate RET[QL] and fix aliases for 16-bit mode ...

I couldn't see how to do this sanely without splitting RETQ from RETL.

Eric says: "sad about the inability to roundtrip them now, but...".
I have no idea what that means, but perhaps it wants preserving in the
commit comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198756 91177308-0d34-0410-b5e6-96231b3b80d8

2014-01-08 12:58:07 +00:00

..

AArch64

[AArch64][NEON] Added SXTL and SXTL2 instruction aliases

2014-01-03 19:20:31 +00:00

ARM

ARM IAS: properly handle expression operands

2014-01-08 03:28:14 +00:00

AsmParser

Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test.

2014-01-05 01:35:51 +00:00

COFF

Add the .secidx test I've forgotten to svn add in 197826

2013-12-20 19:06:50 +00:00

Disassembler

[Sparc] Add support for parsing branch instructions and conditional moves.

2014-01-08 06:14:52 +00:00

ELF

In the ELFWriter when writing aliased (.set) symbols dont blindly

2014-01-07 20:17:03 +00:00

MachO

Fixed a bug in getARMFixupKindMachOInfo() where three ARM fixup kinds

2013-12-13 22:46:54 +00:00

Markup

MC: Simple example parser for MC assembly markup.

2012-10-31 23:24:13 +00:00

Mips

[Mips] TargetStreamer Support for .abicalls and .set pic0.

2014-01-06 23:27:31 +00:00

PowerPC

Convert another llc -filetype=obj test.

2013-10-28 22:17:19 +00:00

Sparc

[SparcV9] Rename operands in some sparc64 instructions so that TableGen can encode them correctly.

2014-01-08 07:47:57 +00:00

SystemZ

[SystemZ] Add MC support for interlocked-access 1 instructions

2013-12-24 15:14:05 +00:00

X86

[x86] Disambiguate RET[QL] and fix aliases for 16-bit mode

2014-01-08 12:58:07 +00:00