Evan Cheng d7e3cc840b Don't be overly aggressive with CSE of "ldr constantpool". If it's a pc-relative ...

value, the "add pc" must be CSE'ed at the same time. We could follow the same
approach as T2 by adding pseudo instructions that combine the ldr + "add pc".
But the better approach is to use movw + movt (which I will enable soon), so
I'll leave this as a TODO.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123949 91177308-0d34-0410-b5e6-96231b3b80d8

2011-01-20 23:55:07 +00:00

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Alpha

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ARM

Don't be overly aggressive with CSE of "ldr constantpool". If it's a pc-relative

2011-01-20 23:55:07 +00:00

Blackfin

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CBackend

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CellSPU

Allow sign-extending of i8 and i16 to i128 on SPU.

2011-01-20 15:49:06 +00:00

CPP

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Generic

fix rdar://8878965, a regression I introduced with the recent

2011-01-18 20:53:04 +00:00

MBlaze

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Mips

Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka

2011-01-18 19:29:17 +00:00

MSP430

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PowerPC

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PTX

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SPARC

Sparc backend: Implements a delay slot filler that attempt to fill delay slots

2011-01-20 05:08:26 +00:00

SystemZ

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Thumb

Sorry, several patches in one.

2011-01-20 08:34:58 +00:00

Thumb2

Add ARM patterns to match EXTRACT_SUBVECTOR nodes.

2011-01-07 04:59:04 +00:00

X86

Expand invalid return values for umulo and smulo. Handle these similarly

2011-01-20 08:54:28 +00:00

XCore

Update tests.

2011-01-16 18:02:57 +00:00

thumb2-mul.ll

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