mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-08-15 22:28:18 +00:00
d860aa62ac
that regalloc doesn't cleverly reuse early arg regs loading later arg regs. This fixes almost all outstanding failures in the pattern isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21086 91177308-0d34-0410-b5e6-96231b3b80d8
TODO: * poor switch statement codegen * load/store to alloca'd array or struct. * implement not-R0 register GPR class * implement scheduling info * implement do-loop pass * implement do-loop -> bdnz transform * implement powerpc-64 for darwin * implement powerpc-64 for aix * use stfiwx in float->int * should hint to the branch select pass that it doesn't need to print the second unconditional branch, so we don't end up with things like: b .LBBl42__2E_expand_function_8_674 ; loopentry.24 b .LBBl42__2E_expand_function_8_42 ; NewDefault b .LBBl42__2E_expand_function_8_42 ; NewDefault Currently failing tests that should pass: * MultiSource |- Applications | `- hbd: miscompilation