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than the scaled register. This makes it more likely that subsequent AddrModeMatcher queries will match the new address the same way as the old, instead of accidentally matching what had been the base register as the new scaled register, and then failing to match the scaled register. This fixes some problems with address-mode sinking multiple muls into a block, which will be a lot more common with some upcoming LoopStrengthReduction changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93935 91177308-0d34-0410-b5e6-96231b3b80d8
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