mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
117 lines
3.2 KiB
LLVM
117 lines
3.2 KiB
LLVM
; addr-01.ll in which the address is also used in a non-address context.
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; The assumption here is that we should match complex addresses where
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; possible, but this might well need to change in future.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; A simple index address.
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define void @f1(i64 %addr, i64 %index, i8 **%dst) {
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; CHECK-LABEL: f1:
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; CHECK: lb %r0, 0(%r3,%r2)
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; CHECK: br %r14
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%add = add i64 %addr, %index
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%ptr = inttoptr i64 %add to i8 *
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%a = load volatile i8 , i8 *%ptr
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store volatile i8 *%ptr, i8 **%dst
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ret void
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}
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; An address with an index and a displacement (order 1).
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define void @f2(i64 %addr, i64 %index, i8 **%dst) {
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; CHECK-LABEL: f2:
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; CHECK: lb %r0, 100(%r3,%r2)
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; CHECK: br %r14
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%add1 = add i64 %addr, %index
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%add2 = add i64 %add1, 100
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%ptr = inttoptr i64 %add2 to i8 *
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%a = load volatile i8 , i8 *%ptr
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store volatile i8 *%ptr, i8 **%dst
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ret void
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}
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; An address with an index and a displacement (order 2).
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define void @f3(i64 %addr, i64 %index, i8 **%dst) {
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; CHECK-LABEL: f3:
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; CHECK: lb %r0, 100(%r3,%r2)
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; CHECK: br %r14
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%add1 = add i64 %addr, 100
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%add2 = add i64 %add1, %index
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%ptr = inttoptr i64 %add2 to i8 *
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%a = load volatile i8 , i8 *%ptr
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store volatile i8 *%ptr, i8 **%dst
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ret void
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}
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; An address with an index and a subtracted displacement (order 1).
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define void @f4(i64 %addr, i64 %index, i8 **%dst) {
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; CHECK-LABEL: f4:
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; CHECK: lb %r0, -100(%r3,%r2)
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; CHECK: br %r14
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%add1 = add i64 %addr, %index
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%add2 = sub i64 %add1, 100
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%ptr = inttoptr i64 %add2 to i8 *
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%a = load volatile i8 , i8 *%ptr
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store volatile i8 *%ptr, i8 **%dst
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ret void
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}
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; An address with an index and a subtracted displacement (order 2).
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define void @f5(i64 %addr, i64 %index, i8 **%dst) {
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; CHECK-LABEL: f5:
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; CHECK: lb %r0, -100(%r3,%r2)
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; CHECK: br %r14
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%add1 = sub i64 %addr, 100
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%add2 = add i64 %add1, %index
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%ptr = inttoptr i64 %add2 to i8 *
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%a = load volatile i8 , i8 *%ptr
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store volatile i8 *%ptr, i8 **%dst
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ret void
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}
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; An address with an index and a displacement added using OR.
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define void @f6(i64 %addr, i64 %index, i8 **%dst) {
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; CHECK-LABEL: f6:
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; CHECK: nill %r2, 65528
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; CHECK: lb %r0, 6(%r3,%r2)
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; CHECK: br %r14
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%aligned = and i64 %addr, -8
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%or = or i64 %aligned, 6
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%add = add i64 %or, %index
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%ptr = inttoptr i64 %add to i8 *
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%a = load volatile i8 , i8 *%ptr
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store volatile i8 *%ptr, i8 **%dst
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ret void
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}
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; Like f6, but without the masking. This OR doesn't count as a displacement.
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define void @f7(i64 %addr, i64 %index, i8 **%dst) {
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; CHECK-LABEL: f7:
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; CHECK: oill %r2, 6
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; CHECK: lb %r0, 0(%r3,%r2)
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; CHECK: br %r14
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%or = or i64 %addr, 6
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%add = add i64 %or, %index
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%ptr = inttoptr i64 %add to i8 *
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%a = load volatile i8 , i8 *%ptr
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store volatile i8 *%ptr, i8 **%dst
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ret void
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}
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; Like f6, but with the OR applied after the index. We don't know anything
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; about the alignment of %add here.
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define void @f8(i64 %addr, i64 %index, i8 **%dst) {
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; CHECK-LABEL: f8:
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; CHECK: nill %r2, 65528
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; CHECK: agr %r2, %r3
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; CHECK: oill %r2, 6
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; CHECK: lb %r0, 0(%r2)
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; CHECK: br %r14
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%aligned = and i64 %addr, -8
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%add = add i64 %aligned, %index
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%or = or i64 %add, 6
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%ptr = inttoptr i64 %or to i8 *
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%a = load volatile i8 , i8 *%ptr
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store volatile i8 *%ptr, i8 **%dst
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ret void
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}
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