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00e08fcaa0
Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215558 91177308-0d34-0410-b5e6-96231b3b80d8
66 lines
2.2 KiB
C++
66 lines
2.2 KiB
C++
//===-- ARMInstrInfo.h - ARM Instruction Information ------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARMINSTRINFO_H
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#define LLVM_LIB_TARGET_ARM_ARMINSTRINFO_H
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#include "ARMBaseInstrInfo.h"
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#include "ARMRegisterInfo.h"
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namespace llvm {
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class ARMSubtarget;
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class ARMInstrInfo : public ARMBaseInstrInfo {
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ARMRegisterInfo RI;
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public:
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explicit ARMInstrInfo(const ARMSubtarget &STI);
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/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
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void getNoopForMachoTarget(MCInst &NopInst) const override;
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// Return the non-pre/post incrementing version of 'Opc'. Return 0
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// if there is not such an opcode.
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unsigned getUnindexedOpcode(unsigned Opc) const override;
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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const ARMRegisterInfo &getRegisterInfo() const override { return RI; }
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/// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
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/// and \p DefIdx.
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/// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
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/// the list is modeled as <Reg:SubReg, SubIdx>.
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/// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
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/// two elements:
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/// - vreg1:sub1, sub0
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/// - vreg2<:0>, sub1
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///
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/// \returns true if it is possible to build such an input sequence
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/// with the pair \p MI, \p DefIdx. False otherwise.
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///
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/// \pre MI.isRegSequenceLike().
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bool getRegSequenceLikeInputs(
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const MachineInstr &MI, unsigned DefIdx,
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SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override;
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private:
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void expandLoadStackGuard(MachineBasicBlock::iterator MI,
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Reloc::Model RM) const override;
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};
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}
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#endif
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