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https://github.com/c64scene-ar/llvm-6502.git
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6fe7acaaf8
We don't have a good way to detect most situations where DS offsets are usable on SI, so add an option to force using them even if unsafe for debugging performance problems. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241462 91177308-0d34-0410-b5e6-96231b3b80d8
71 lines
3.7 KiB
LLVM
71 lines
3.7 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefix=SI --check-prefix=CHECK %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefix=CI --check-prefix=CHECK %s
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; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -mattr=+load-store-opt,+unsafe-ds-offset-folding < %s | FileCheck -check-prefix=CI --check-prefix=CHECK %s
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declare i32 @llvm.r600.read.tidig.x() #0
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declare void @llvm.AMDGPU.barrier.local() #1
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; Function Attrs: nounwind
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; CHECK-LABEL: {{^}}signed_ds_offset_addressing_loop:
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; CHECK: BB0_1:
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; CHECK: v_add_i32_e32 [[VADDR:v[0-9]+]],
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; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR]]
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; SI-DAG: v_add_i32_e32 [[VADDR4:v[0-9]+]], 4, [[VADDR]]
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; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR4]]
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; SI-DAG: v_add_i32_e32 [[VADDR0x80:v[0-9]+]], 0x80, [[VADDR]]
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; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x80]]
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; SI-DAG: v_add_i32_e32 [[VADDR0x84:v[0-9]+]], 0x84, [[VADDR]]
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; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x84]]
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; SI-DAG: v_add_i32_e32 [[VADDR0x100:v[0-9]+]], 0x100, [[VADDR]]
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; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x100]]
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; CI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset1:1
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; CI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset0:32 offset1:33
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; CI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR]] offset:256
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; CHECK: s_endpgm
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define void @signed_ds_offset_addressing_loop(float addrspace(1)* noalias nocapture %out, float addrspace(3)* noalias nocapture readonly %lptr, i32 %n) #2 {
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entry:
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #0
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%mul = shl nsw i32 %x.i, 1
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%sum.03 = phi float [ 0.000000e+00, %entry ], [ %add13, %for.body ]
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%offset.02 = phi i32 [ %mul, %entry ], [ %add14, %for.body ]
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%k.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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tail call void @llvm.AMDGPU.barrier.local() #1
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%arrayidx = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %offset.02
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%tmp = load float, float addrspace(3)* %arrayidx, align 4
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%add1 = add nsw i32 %offset.02, 1
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%arrayidx2 = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %add1
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%tmp1 = load float, float addrspace(3)* %arrayidx2, align 4
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%add3 = add nsw i32 %offset.02, 32
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%arrayidx4 = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %add3
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%tmp2 = load float, float addrspace(3)* %arrayidx4, align 4
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%add5 = add nsw i32 %offset.02, 33
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%arrayidx6 = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %add5
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%tmp3 = load float, float addrspace(3)* %arrayidx6, align 4
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%add7 = add nsw i32 %offset.02, 64
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%arrayidx8 = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %add7
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%tmp4 = load float, float addrspace(3)* %arrayidx8, align 4
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%add9 = fadd float %tmp, %tmp1
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%add10 = fadd float %add9, %tmp2
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%add11 = fadd float %add10, %tmp3
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%add12 = fadd float %add11, %tmp4
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%add13 = fadd float %sum.03, %add12
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%inc = add nsw i32 %k.01, 1
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%add14 = add nsw i32 %offset.02, 97
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%exitcond = icmp eq i32 %inc, 8
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body
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%tmp5 = sext i32 %x.i to i64
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%arrayidx15 = getelementptr inbounds float, float addrspace(1)* %out, i64 %tmp5
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store float %add13, float addrspace(1)* %arrayidx15, align 4
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { noduplicate nounwind }
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attributes #2 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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