Dan Gohman 764fd0cbc8 Simplify ReduceLoadWidth's logic: it doesn't need several different ...

special cases after producing the new reduced-width load, because the
new load already has the needed adjustments built into it. This fixes
several bugs due to the special cases, including PR3317.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62692 91177308-0d34-0410-b5e6-96231b3b80d8

2009-01-21 15:17:51 +00:00

..

CallingConvLower.cpp

Add "inreg" field to CallSDNode (doesn't increase

2008-09-26 19:31:26 +00:00

CMakeLists.txt

Experimental post-pass scheduling support. Post-pass scheduling

2008-11-19 23:18:57 +00:00

DAGCombiner.cpp

Simplify ReduceLoadWidth's logic: it doesn't need several different

2009-01-21 15:17:51 +00:00

FastISel.cpp

Verify debug info.

2009-01-19 23:21:49 +00:00

LegalizeDAG.cpp

CellSPU:

2009-01-21 04:58:48 +00:00

LegalizeFloatTypes.cpp

Cleanup whitespace and comments, and tweak some

2009-01-21 09:00:29 +00:00

LegalizeIntegerTypes.cpp

Cleanup whitespace and comments, and tweak some

2009-01-21 09:00:29 +00:00

LegalizeTypes.cpp

Cleanup whitespace and comments, and tweak some

2009-01-21 09:00:29 +00:00

LegalizeTypes.h

Cleanup whitespace and comments, and tweak some

2009-01-21 09:00:29 +00:00

LegalizeTypesGeneric.cpp

Preserve SourceValue information when lowering produces multiple loads from

2008-12-16 18:25:36 +00:00

LegalizeVectorTypes.cpp

Added missing support to widen an operand from a bit convert.

2009-01-15 22:43:38 +00:00

Makefile

Removed trailing whitespace from Makefiles.

2009-01-09 16:44:42 +00:00

ScheduleDAGFast.cpp

Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph

2009-01-15 19:20:50 +00:00

ScheduleDAGList.cpp

Initial hazard recognizer support in post-pass scheduling. This includes

2009-01-16 01:33:36 +00:00

ScheduleDAGRRList.cpp

Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph

2009-01-15 19:20:50 +00:00

ScheduleDAGSDNodes.cpp

CreateVirtualRegisters does trivial copy coalescing. If a node def is used by a single CopyToReg, it reuses the virtual register assigned to the CopyToReg. This won't work for SDNode that is a clone or is itself cloned. Disable this optimization for those nodes or it can end up with non-SSA machine instructions.

2009-01-16 20:57:18 +00:00

ScheduleDAGSDNodesEmit.cpp

Instead of adding dependence edges between terminator instructions

2009-01-16 22:10:20 +00:00

SelectionDAG.cpp

Remove SDNode's virtual destructor. This makes it impossible for

2009-01-19 22:39:36 +00:00

SelectionDAGBuild.cpp

Cleanup whitespace and comments, and tweak some

2009-01-21 09:00:29 +00:00

SelectionDAGBuild.h

Initial checkin of APInt'ififcation of switch lowering

2008-12-23 22:25:27 +00:00

SelectionDAGISel.cpp

Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well.

2009-01-20 19:12:24 +00:00

SelectionDAGPrinter.cpp

Use DebugInfo interface to lower dbg_* intrinsics.

2009-01-13 00:35:13 +00:00

TargetLowering.cpp

Few targets like PIC16 wants libcall generation for illegal type i16.

2009-01-18 18:25:27 +00:00