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dc07321164788a885364acca5b0e2b3e6a7d615d
llvm-6502/test/CodeGen
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Kalle Raiskila 989621f1f8 Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 10:05:01 +00:00
..
Alpha
…
ARM
Revert r131152, r129796, r129761. This code is currently considered
2011-09-01 23:07:08 +00:00
Blackfin
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CBackend
Revert r137134. It breaks some code as Eli pointed out.
2011-08-09 18:56:35 +00:00
CellSPU
Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.
2011-09-02 10:05:01 +00:00
CPP
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Generic
XFAIL this test on arm until the backend is fixed.
2011-09-01 18:40:03 +00:00
MBlaze
…
Mips
Revert r131152, r129796, r129761. This code is currently considered
2011-09-01 23:07:08 +00:00
MSP430
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PowerPC
Update more tests to the new EH scheme.
2011-08-31 21:04:11 +00:00
PTX
PTX: Add initial support for device function calls
2011-08-09 17:36:31 +00:00
SPARC
…
SystemZ
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Thumb
Revert r131152, r129796, r129761. This code is currently considered
2011-09-01 23:07:08 +00:00
Thumb2
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical
2011-08-30 01:34:54 +00:00
X86
This test depends on cmov being available.
2011-09-01 18:40:01 +00:00
XCore
Add Uses=[SP] to call instructions. This fixes a miscompilation with a
2011-08-24 13:32:43 +00:00
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