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llvm-6502/test/CodeGen/Mips
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Daniel Sanders 77ae274ae7 [mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6 
Summary:
There is no change to the restrictions, just the result register is stored
once in the encoding rather than twice. The rt field is zero in
MIPS32r6/MIPS64r6.

Depends on D4119

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4120

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211019 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-16 13:18:59 +00:00
..
cconv
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Fast-ISel
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mips32r6
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mips64r6
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msa
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2008-06-05-Carry.ll
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2008-07-03-SRet.ll
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2008-07-06-fadd64.ll
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2008-07-07-Float2Int.ll
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2008-07-07-FPExtend.ll
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2008-07-07-IntDoubleConvertions.ll
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2008-07-15-InternalConstant.ll
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2008-07-15-SmallSection.ll
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2008-07-16-SignExtInReg.ll
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2008-07-22-Cstpool.ll
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2008-07-23-fpcmp.ll
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2008-07-29-icmp.ll
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2008-07-31-fcopysign.ll
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2008-08-01-AsmInline.ll
[mips][mips64r6] Improve tests affected by the changes to multiplies and divides
2014-06-11 15:48:00 +00:00
2008-08-03-fabs64.ll
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2008-08-03-ReturnDouble.ll
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2008-08-04-Bitconvert.ll
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2008-08-06-Alloca.ll
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2008-08-07-CC.ll
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2008-08-07-FPRound.ll
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2008-08-08-bswap.ll
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2008-08-08-ctlz.ll
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2008-10-13-LegalizerBug.ll
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2008-11-10-xint_to_fp.ll
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2009-11-16-CstPoolLoad.ll
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2010-07-20-Switch.ll
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2010-11-09-CountLeading.ll
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2010-11-09-Mul.ll
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2011-05-26-BranchKillsVreg.ll
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2012-12-12-ExpandMemcpy.ll
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2013-11-18-fp64-const0.ll
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abicalls.ll
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addc.ll
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addi.ll
[Mips] Adjust float ABI settings in case of MIPS16 mode.
2013-11-19 12:20:17 +00:00
addressing-mode.ll
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align16.ll
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alloca16.ll
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alloca.ll
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analyzebranch.ll
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and1.ll
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asm-large-immediate.ll
The inline asm operand modifier 'n' is suppose
2012-06-21 21:37:54 +00:00
atomic.ll
[mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6.
2014-06-16 13:13:03 +00:00
atomicops.ll
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beqzc1.ll
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beqzc.ll
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biggot.ll
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blez_bgez.ll
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blockaddr.ll
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br-jmp.ll
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brconeq.ll
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brconeqk.ll
Add conditional branch instructions and their patterns.
2012-10-17 22:29:54 +00:00
brconeqz.ll
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brconge.ll
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brcongt.ll
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brconle.ll
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brconlt.ll
Add conditional branch instructions and their patterns.
2012-10-17 22:29:54 +00:00
brconne.ll
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brconnek.ll
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brconnez.ll
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brdelayslot.ll
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brind.ll
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brsize3.ll
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brsize3a.ll
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bswap.ll
[mips] Check emitted code for llvm.bswap.i32 on MIPS16/MIPS64 and llvm.bswap.i64 on MIPS16.
2014-03-31 11:00:04 +00:00
buildpairextractelementf64.ll
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cache-intrinsic.ll
Add @llvm.clear_cache builtin
2014-03-26 12:52:28 +00:00
call-optimization.ll
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check-noat.ll
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ci2.ll
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cmov.ll
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cmplarge.ll
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const1.ll
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const4a.ll
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const6.ll
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const6a.ll
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const-mult.ll
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constantfp0.ll
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countleading.ll
[mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6
2014-06-16 13:18:59 +00:00
cprestore.ll
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ctlz.ll
[Mips] Adjust float ABI settings in case of MIPS16 mode.
2013-11-19 12:20:17 +00:00
DbgValueOtherTargets.test
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disable-tail-merge.ll
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div_rem.ll
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div.ll
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divrem.ll
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divu_remu.ll
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divu.ll
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double2int.ll
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dsp-patterns-cmp-vselect.ll
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dsp-patterns.ll
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dsp-r1.ll
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dsp-r2.ll
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dsp-vec-load-store.ll
[mips] Expand vector truncating stores and extending loads.
2013-08-02 19:23:33 +00:00
eh-dwarf-cfa.ll
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eh-return32.ll
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eh-return64.ll
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eh.ll
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ehframe-indirect.ll
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elf_eflags.ll
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emit-big-cst.ll
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ex2.ll
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extins.ll
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f16abs.ll
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fabs.ll
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fastcc.ll
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fcmp.ll
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fcopysign-f32-f64.ll
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fcopysign.ll
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fixdfsf.ll
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fmadd1.ll
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fneg.ll
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fp16instrinsmc.ll
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fp16mix.ll
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fp16static.ll
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fp-indexed-ls.ll
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fp-spill-reload.ll
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fpbr.ll
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fpneeded.ll
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fpnotneeded.ll
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fptr2.ll
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frame-address.ll
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frem.ll
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global-address.ll
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global-pointer-reg.ll
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gpreg-lazy-binding.ll
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gprestore.ll
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helloworld.ll
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hf1_body.ll
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hf16_1.ll
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hf16call32_body.ll
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hf16call32.ll
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hfptrcall.ll
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i32k.ll
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i64arg.ll
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imm.ll
Add a test case for r146900.
2011-12-19 20:24:28 +00:00
indirectcall.ll
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init-array.ll
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inlineasm64.ll
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inlineasm_constraint.ll
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inlineasm-cnstrnt-bad-I-1.ll
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inlineasm-cnstrnt-bad-J.ll
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inlineasm-cnstrnt-bad-K.ll
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inlineasm-cnstrnt-bad-L.ll
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inlineasm-cnstrnt-bad-N.ll
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inlineasm-cnstrnt-bad-O.ll
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inlineasm-cnstrnt-bad-P.ll
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inlineasm-cnstrnt-reg64.ll
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inlineasm-cnstrnt-reg.ll
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inlineasm-operand-code.ll
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inlineasmmemop.ll
Mips specific inline asm memory operand modifier test case
2013-04-11 19:39:19 +00:00
int-to-float-conversion.ll
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internalfunc.ll
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jtstat.ll
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l3mc.ll
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largeimm1.ll
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largeimmprinting.ll
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lazy-binding.ll
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lb1.ll
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lbu1.ll
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lcb2.ll
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lcb3c.ll
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lcb4a.ll
final patch for very long conditional branches for mips16 constant islands.
2013-12-03 23:42:51 +00:00
lcb5.ll
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lh1.ll
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lhu1.ll
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lit.local.cfg
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llcarry.ll
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load-store-left-right.ll
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longbranch.ll
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machineverifier.ll
Make machine verifier check the first instruction of the last bundle instead of
2012-06-14 20:51:13 +00:00
madd-msub.ll
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mature-mc-support.ll
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mbrsize4a.ll
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memcpy.ll
Set a higher value for maxStoresPerMemcpy in MipsISelLowering.cpp.
2012-06-13 19:33:32 +00:00
micromips-atomic.ll
Fixed operand of SC microMIPS instruction.
2014-02-28 18:22:56 +00:00
micromips-directives.ll
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micromips-jal.ll
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micromips-load-effective-address.ll
Test case micromips-load-effective-address.s renamed to micromips-load-effective-address.ll and moved to test/CodeGen/Mips.
2014-01-14 16:26:47 +00:00
mips16_32_1.ll
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mips16_32_3.ll
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mips16_32_4.ll
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mips16_32_5.ll
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mips16_32_6.ll
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mips16_32_7.ll
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mips16_32_8.ll
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mips16_32_9.ll
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mips16_32_10.ll
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mips16_fpret.ll
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mips16-hf-attr.ll
[Mips] Does not take in account 'use-soft-float' attribute's value when
2013-12-25 17:00:27 +00:00
mips16ex.ll
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mips16fpe.ll
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mips64-f128-call.ll
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mips64-f128.ll
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mips64-libcall.ll
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mips64-sret.ll
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mips64directive.ll
[mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point
2014-04-14 16:00:28 +00:00
mips64ext.ll
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mips64extins.ll
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mips64fpimm0.ll
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mips64fpldst.ll
[mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point
2014-04-14 16:00:28 +00:00
mips64imm.ll
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mips64instrs.ll
[mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6
2014-06-16 13:18:59 +00:00
mips64intldst.ll
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mips64lea.ll
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mips64muldiv.ll
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mips64shift.ll
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mipslopat.ll
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misha.ll
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mno-ldc1-sdc1.ll
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mul.ll
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mulll.ll
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mulull.ll
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nacl-align.ll
Moved test file from test/MC/Mips to test/CodeGen/Mips.
2014-03-07 22:08:46 +00:00
nacl-branch-delay.ll
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nacl-reserved-regs.ll
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neg1.ll
1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
2012-08-03 22:57:02 +00:00
nomips16.ll
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not1.ll
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null.ll
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o32_cc_byval.ll
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o32_cc_vararg.ll
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o32_cc.ll
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octeon_popcnt.ll
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octeon.ll
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optimize-fp-math.ll
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optimize-pic-o0.ll
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or1.ll
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powif64_16.ll
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prevent-hoisting.ll
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private.ll
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ra-allocatable.ll
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rdhwr-directives.ll
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rem.ll
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remat-immed-load.ll
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remu.ll
Div, Rem int/unsigned int
2012-10-12 02:01:09 +00:00
return_address.ll
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return-vector.ll
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rotate.ll
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s2rem.ll
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sb1.ll
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sel1c.ll
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sel2c.ll
[mips] Small code generation improvement for conditional operator (select)
2013-12-05 12:07:05 +00:00
select.ll
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selectcc.ll
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seleq.ll
Beginning of expanding all current mips16 macro/pseudo instruction sequences.
2013-02-18 00:59:04 +00:00
seleqk.ll
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selgek.ll
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selgt.ll
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selle.ll
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selltk.ll
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selne.ll
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selnek.ll
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selpat.ll
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selTBteqzCmpi.ll
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selTBtnezCmpi.ll
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selTBtnezSlti.ll
Expand mips16 SelT form pseudso/macros.
2013-02-22 05:10:51 +00:00
setcc-se.ll
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seteq.ll
Expand pseudos/macros:
2013-02-20 05:45:15 +00:00
seteqz.ll
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setge.ll
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setgek.ll
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setle.ll
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setlt.ll
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setltk.ll
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setne.ll
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setuge.ll
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setugt.ll
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setule.ll
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setult.ll
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setultk.ll
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sh1.ll
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shift-parts.ll
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simplebr.ll
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sint-fp-store_pattern.ll
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sitofp-selectcc-opt.ll
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sll1.ll
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sll2.ll
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small-section-reserve-gp.ll
In MipsDAGToDAGISel::SelectAddr, fold add node into address operand, if its
2012-08-24 20:21:49 +00:00
spill-copy-acreg.ll
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sr1.ll
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sra1.ll
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sra2.ll
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srl1.ll
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srl2.ll
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stack-alignment.ll
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stackcoloring.ll
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stacksize.ll
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start-asm-file.ll
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stchar.ll
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stldst.ll
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sub1.ll
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sub2.ll
1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
2012-08-03 22:57:02 +00:00
swzero.ll
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tail16.ll
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tailcall.ll
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tls16_2.ll
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tls16.ll
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tls-alias.ll
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tls-models.ll
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tls.ll
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tnaked.ll
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trap1.ll
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trap.ll
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uitofp.ll
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ul1.ll
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unalignedload.ll
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vector-load-store.ll
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vector-setcc.ll
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weak.ll
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xor1.ll
1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
2012-08-03 22:57:02 +00:00
zeroreg.ll
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