Bob Wilson dc66edaced Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee ...

that the high halfword is zero.  The shift need not be exactly 16 bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111196 91177308-0d34-0410-b5e6-96231b3b80d8

2010-08-16 22:26:55 +00:00

..

Alpha

PR7774: Fix undefined shifts in Alpha backend. As a bonus, this actually

2010-08-01 21:13:28 +00:00

ARM

Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee

2010-08-16 22:26:55 +00:00

Blackfin

…

CBackend

…

CellSPU

Have SPU handle halfvec stores aligned by 8 bytes.

2010-08-09 16:33:00 +00:00

CPP

…

Generic

…

MBlaze

…

Mips

…

MSP430

…

PIC16

…

PowerPC

PR7781: Fix incorrect shifting in PPCTargetLowering::LowerBUILD_VECTOR.

2010-08-02 00:18:19 +00:00

SPARC

…

SystemZ

…

Thumb

Fix test and re-enable it.

2010-08-11 17:25:51 +00:00

Thumb2

Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee

2010-08-16 22:26:55 +00:00

X86

Test expects SSE, give him SSE.

2010-08-15 23:32:03 +00:00

XCore

…