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7c3ecb6838
uses several kinds of opcode values which are not declared within that enum. This fixes PR5946. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92794 91177308-0d34-0410-b5e6-96231b3b80d8
317 lines
11 KiB
C++
317 lines
11 KiB
C++
//===-- FastISel.h - Definition of the FastISel class ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the FastISel class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_FASTISEL_H
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#define LLVM_CODEGEN_FASTISEL_H
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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namespace llvm {
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class AllocaInst;
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class ConstantFP;
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class Instruction;
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class MachineBasicBlock;
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class MachineConstantPool;
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class MachineFunction;
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class MachineFrameInfo;
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class MachineModuleInfo;
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class DwarfWriter;
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class MachineRegisterInfo;
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class TargetData;
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class TargetInstrInfo;
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class TargetLowering;
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class TargetMachine;
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class TargetRegisterClass;
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/// FastISel - This is a fast-path instruction selection class that
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/// generates poor code and doesn't support illegal types or non-trivial
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/// lowering, but runs quickly.
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class FastISel {
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protected:
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MachineBasicBlock *MBB;
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DenseMap<const Value *, unsigned> LocalValueMap;
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DenseMap<const Value *, unsigned> &ValueMap;
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DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
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DenseMap<const AllocaInst *, int> &StaticAllocaMap;
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#ifndef NDEBUG
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SmallSet<Instruction*, 8> &CatchInfoLost;
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#endif
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MachineFunction &MF;
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MachineModuleInfo *MMI;
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DwarfWriter *DW;
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MachineRegisterInfo &MRI;
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MachineFrameInfo &MFI;
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MachineConstantPool &MCP;
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DebugLoc DL;
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const TargetMachine &TM;
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const TargetData &TD;
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const TargetInstrInfo &TII;
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const TargetLowering &TLI;
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public:
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/// startNewBlock - Set the current block to which generated machine
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/// instructions will be appended, and clear the local CSE map.
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///
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void startNewBlock(MachineBasicBlock *mbb) {
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setCurrentBlock(mbb);
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LocalValueMap.clear();
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}
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/// setCurrentBlock - Set the current block to which generated machine
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/// instructions will be appended.
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///
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void setCurrentBlock(MachineBasicBlock *mbb) {
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MBB = mbb;
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}
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/// setCurDebugLoc - Set the current debug location information, which is used
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/// when creating a machine instruction.
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///
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void setCurDebugLoc(DebugLoc dl) { DL = dl; }
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/// getCurDebugLoc() - Return current debug location information.
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DebugLoc getCurDebugLoc() const { return DL; }
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/// SelectInstruction - Do "fast" instruction selection for the given
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/// LLVM IR instruction, and append generated machine instructions to
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/// the current block. Return true if selection was successful.
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///
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bool SelectInstruction(Instruction *I);
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/// SelectOperator - Do "fast" instruction selection for the given
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/// LLVM IR operator (Instruction or ConstantExpr), and append
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/// generated machine instructions to the current block. Return true
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/// if selection was successful.
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///
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bool SelectOperator(User *I, unsigned Opcode);
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/// getRegForValue - Create a virtual register and arrange for it to
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/// be assigned the value for the given LLVM value.
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unsigned getRegForValue(Value *V);
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/// lookUpRegForValue - Look up the value to see if its value is already
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/// cached in a register. It may be defined by instructions across blocks or
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/// defined locally.
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unsigned lookUpRegForValue(Value *V);
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/// getRegForGEPIndex - This is a wrapper around getRegForValue that also
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/// takes care of truncating or sign-extending the given getelementptr
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/// index value.
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unsigned getRegForGEPIndex(Value *V);
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virtual ~FastISel();
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protected:
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FastISel(MachineFunction &mf,
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MachineModuleInfo *mmi,
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DwarfWriter *dw,
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DenseMap<const Value *, unsigned> &vm,
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DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
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DenseMap<const AllocaInst *, int> &am
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#ifndef NDEBUG
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, SmallSet<Instruction*, 8> &cil
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#endif
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);
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/// TargetSelectInstruction - This method is called by target-independent
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/// code when the normal FastISel process fails to select an instruction.
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/// This gives targets a chance to emit code for anything that doesn't
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/// fit into FastISel's framework. It returns true if it was successful.
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///
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virtual bool
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TargetSelectInstruction(Instruction *I) = 0;
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/// FastEmit_r - This method is called by target-independent code
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/// to request that an instruction with the given type and opcode
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/// be emitted.
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virtual unsigned FastEmit_(MVT VT,
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MVT RetVT,
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unsigned Opcode);
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/// FastEmit_r - This method is called by target-independent code
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/// to request that an instruction with the given type, opcode, and
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/// register operand be emitted.
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///
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virtual unsigned FastEmit_r(MVT VT,
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MVT RetVT,
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unsigned Opcode, unsigned Op0);
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/// FastEmit_rr - This method is called by target-independent code
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/// to request that an instruction with the given type, opcode, and
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/// register operands be emitted.
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///
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virtual unsigned FastEmit_rr(MVT VT,
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MVT RetVT,
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unsigned Opcode,
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unsigned Op0, unsigned Op1);
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/// FastEmit_ri - This method is called by target-independent code
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/// to request that an instruction with the given type, opcode, and
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/// register and immediate operands be emitted.
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///
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virtual unsigned FastEmit_ri(MVT VT,
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MVT RetVT,
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unsigned Opcode,
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unsigned Op0, uint64_t Imm);
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/// FastEmit_rf - This method is called by target-independent code
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/// to request that an instruction with the given type, opcode, and
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/// register and floating-point immediate operands be emitted.
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///
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virtual unsigned FastEmit_rf(MVT VT,
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MVT RetVT,
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unsigned Opcode,
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unsigned Op0, ConstantFP *FPImm);
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/// FastEmit_rri - This method is called by target-independent code
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/// to request that an instruction with the given type, opcode, and
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/// register and immediate operands be emitted.
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///
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virtual unsigned FastEmit_rri(MVT VT,
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MVT RetVT,
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unsigned Opcode,
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unsigned Op0, unsigned Op1, uint64_t Imm);
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/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
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/// to emit an instruction with an immediate operand using FastEmit_ri.
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/// If that fails, it materializes the immediate into a register and try
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/// FastEmit_rr instead.
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unsigned FastEmit_ri_(MVT VT,
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unsigned Opcode,
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unsigned Op0, uint64_t Imm,
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MVT ImmType);
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/// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
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/// to emit an instruction with an immediate operand using FastEmit_rf.
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/// If that fails, it materializes the immediate into a register and try
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/// FastEmit_rr instead.
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unsigned FastEmit_rf_(MVT VT,
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unsigned Opcode,
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unsigned Op0, ConstantFP *FPImm,
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MVT ImmType);
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/// FastEmit_i - This method is called by target-independent code
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/// to request that an instruction with the given type, opcode, and
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/// immediate operand be emitted.
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virtual unsigned FastEmit_i(MVT VT,
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MVT RetVT,
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unsigned Opcode,
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uint64_t Imm);
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/// FastEmit_f - This method is called by target-independent code
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/// to request that an instruction with the given type, opcode, and
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/// floating-point immediate operand be emitted.
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virtual unsigned FastEmit_f(MVT VT,
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MVT RetVT,
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unsigned Opcode,
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ConstantFP *FPImm);
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/// FastEmitInst_ - Emit a MachineInstr with no operands and a
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/// result register in the given register class.
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///
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unsigned FastEmitInst_(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC);
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/// FastEmitInst_r - Emit a MachineInstr with one register operand
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/// and a result register in the given register class.
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///
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unsigned FastEmitInst_r(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0);
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/// FastEmitInst_rr - Emit a MachineInstr with two register operands
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/// and a result register in the given register class.
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///
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unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, unsigned Op1);
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/// FastEmitInst_ri - Emit a MachineInstr with two register operands
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/// and a result register in the given register class.
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///
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unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, uint64_t Imm);
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/// FastEmitInst_rf - Emit a MachineInstr with two register operands
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/// and a result register in the given register class.
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///
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unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, ConstantFP *FPImm);
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/// FastEmitInst_rri - Emit a MachineInstr with two register operands,
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/// an immediate, and a result register in the given register class.
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///
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unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, unsigned Op1, uint64_t Imm);
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/// FastEmitInst_i - Emit a MachineInstr with a single immediate
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/// operand, and a result register in the given register class.
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unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
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const TargetRegisterClass *RC,
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uint64_t Imm);
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/// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
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/// from a specified index of a superregister to a specified type.
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unsigned FastEmitInst_extractsubreg(MVT RetVT,
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unsigned Op0, uint32_t Idx);
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/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
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/// with all but the least significant bit set to zero.
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unsigned FastEmitZExtFromI1(MVT VT,
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unsigned Op);
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/// FastEmitBranch - Emit an unconditional branch to the given block,
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/// unless it is the immediate (fall-through) successor, and update
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/// the CFG.
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void FastEmitBranch(MachineBasicBlock *MBB);
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unsigned UpdateValueMap(Value* I, unsigned Reg);
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unsigned createResultReg(const TargetRegisterClass *RC);
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/// TargetMaterializeConstant - Emit a constant in a register using
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/// target-specific logic, such as constant pool loads.
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virtual unsigned TargetMaterializeConstant(Constant* C) {
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return 0;
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}
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/// TargetMaterializeAlloca - Emit an alloca address in a register using
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/// target-specific logic.
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virtual unsigned TargetMaterializeAlloca(AllocaInst* C) {
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return 0;
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}
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private:
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bool SelectBinaryOp(User *I, unsigned ISDOpcode);
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bool SelectFNeg(User *I);
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bool SelectGetElementPtr(User *I);
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bool SelectCall(User *I);
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bool SelectBitCast(User *I);
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bool SelectCast(User *I, unsigned Opcode);
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};
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}
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#endif
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